VirtualBox

source: vbox/trunk/include/VBox/hwacc_svm.h@ 12702

Last change on this file since 12702 was 12702, checked in by vboxsync, 16 years ago

#1865: HWACCM - alignment fix+check for 32-bit gcc, doxygen.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 24.1 KB
Line 
1/** @file
2 * HWACCM - SVM Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_svm_h
31#define ___VBox_svm_h
32
33#include <VBox/types.h>
34#include <VBox/err.h>
35#include <iprt/assert.h>
36#include <iprt/asm.h>
37
38/** @defgroup grp_svm svm Types and Definitions
39 * @ingroup grp_hwaccm
40 * @{
41 */
42
43/** @name SVM features for cpuid 0x8000000a
44 * @{
45 */
46#define AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
47#define AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
48#define AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
49#define AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
50#define AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE RT_BIT(9)
51/** @} */
52
53
54/** @name SVM Basic Exit Reasons.
55 * @{
56 */
57/** Invalid guest state in VMCB. */
58#define SVM_EXIT_INVALID -1
59/** Read from CR0-CR15. */
60#define SVM_EXIT_READ_CR0 0x0
61#define SVM_EXIT_READ_CR1 0x1
62#define SVM_EXIT_READ_CR2 0x2
63#define SVM_EXIT_READ_CR3 0x3
64#define SVM_EXIT_READ_CR4 0x4
65#define SVM_EXIT_READ_CR5 0x5
66#define SVM_EXIT_READ_CR6 0x6
67#define SVM_EXIT_READ_CR7 0x7
68#define SVM_EXIT_READ_CR8 0x8
69#define SVM_EXIT_READ_CR9 0x9
70#define SVM_EXIT_READ_CR10 0xA
71#define SVM_EXIT_READ_CR11 0xB
72#define SVM_EXIT_READ_CR12 0xC
73#define SVM_EXIT_READ_CR13 0xD
74#define SVM_EXIT_READ_CR14 0xE
75#define SVM_EXIT_READ_CR15 0xF
76/** Writes to CR0-CR15. */
77#define SVM_EXIT_WRITE_CR0 0x10
78#define SVM_EXIT_WRITE_CR1 0x11
79#define SVM_EXIT_WRITE_CR2 0x12
80#define SVM_EXIT_WRITE_CR3 0x13
81#define SVM_EXIT_WRITE_CR4 0x14
82#define SVM_EXIT_WRITE_CR5 0x15
83#define SVM_EXIT_WRITE_CR6 0x16
84#define SVM_EXIT_WRITE_CR7 0x17
85#define SVM_EXIT_WRITE_CR8 0x18
86#define SVM_EXIT_WRITE_CR9 0x19
87#define SVM_EXIT_WRITE_CR10 0x1A
88#define SVM_EXIT_WRITE_CR11 0x1B
89#define SVM_EXIT_WRITE_CR12 0x1C
90#define SVM_EXIT_WRITE_CR13 0x1D
91#define SVM_EXIT_WRITE_CR14 0x1E
92#define SVM_EXIT_WRITE_CR15 0x1F
93/** Read from DR0-DR15. */
94#define SVM_EXIT_READ_DR0 0x20
95#define SVM_EXIT_READ_DR1 0x21
96#define SVM_EXIT_READ_DR2 0x22
97#define SVM_EXIT_READ_DR3 0x23
98#define SVM_EXIT_READ_DR4 0x24
99#define SVM_EXIT_READ_DR5 0x25
100#define SVM_EXIT_READ_DR6 0x26
101#define SVM_EXIT_READ_DR7 0x27
102#define SVM_EXIT_READ_DR8 0x28
103#define SVM_EXIT_READ_DR9 0x29
104#define SVM_EXIT_READ_DR10 0x2A
105#define SVM_EXIT_READ_DR11 0x2B
106#define SVM_EXIT_READ_DR12 0x2C
107#define SVM_EXIT_READ_DR13 0x2D
108#define SVM_EXIT_READ_DR14 0x2E
109#define SVM_EXIT_READ_DR15 0x2F
110/** Writes to DR0-DR15. */
111#define SVM_EXIT_WRITE_DR0 0x30
112#define SVM_EXIT_WRITE_DR1 0x31
113#define SVM_EXIT_WRITE_DR2 0x32
114#define SVM_EXIT_WRITE_DR3 0x33
115#define SVM_EXIT_WRITE_DR4 0x34
116#define SVM_EXIT_WRITE_DR5 0x35
117#define SVM_EXIT_WRITE_DR6 0x36
118#define SVM_EXIT_WRITE_DR7 0x37
119#define SVM_EXIT_WRITE_DR8 0x38
120#define SVM_EXIT_WRITE_DR9 0x39
121#define SVM_EXIT_WRITE_DR10 0x3A
122#define SVM_EXIT_WRITE_DR11 0x3B
123#define SVM_EXIT_WRITE_DR12 0x3C
124#define SVM_EXIT_WRITE_DR13 0x3D
125#define SVM_EXIT_WRITE_DR14 0x3E
126#define SVM_EXIT_WRITE_DR15 0x3F
127/* Exception 0-31. */
128#define SVM_EXIT_EXCEPTION_0 0x40
129#define SVM_EXIT_EXCEPTION_1 0x41
130#define SVM_EXIT_EXCEPTION_2 0x42
131#define SVM_EXIT_EXCEPTION_3 0x43
132#define SVM_EXIT_EXCEPTION_4 0x44
133#define SVM_EXIT_EXCEPTION_5 0x45
134#define SVM_EXIT_EXCEPTION_6 0x46
135#define SVM_EXIT_EXCEPTION_7 0x47
136#define SVM_EXIT_EXCEPTION_8 0x48
137#define SVM_EXIT_EXCEPTION_9 0x49
138#define SVM_EXIT_EXCEPTION_A 0x4A
139#define SVM_EXIT_EXCEPTION_B 0x4B
140#define SVM_EXIT_EXCEPTION_C 0x4C
141#define SVM_EXIT_EXCEPTION_D 0x4D
142#define SVM_EXIT_EXCEPTION_E 0x4E
143#define SVM_EXIT_EXCEPTION_F 0x4F
144#define SVM_EXIT_EXCEPTION_10 0x50
145#define SVM_EXIT_EXCEPTION_11 0x51
146#define SVM_EXIT_EXCEPTION_12 0x52
147#define SVM_EXIT_EXCEPTION_13 0x53
148#define SVM_EXIT_EXCEPTION_14 0x54
149#define SVM_EXIT_EXCEPTION_15 0x55
150#define SVM_EXIT_EXCEPTION_16 0x56
151#define SVM_EXIT_EXCEPTION_17 0x57
152#define SVM_EXIT_EXCEPTION_18 0x58
153#define SVM_EXIT_EXCEPTION_19 0x59
154#define SVM_EXIT_EXCEPTION_1A 0x5A
155#define SVM_EXIT_EXCEPTION_1B 0x5B
156#define SVM_EXIT_EXCEPTION_1C 0x5C
157#define SVM_EXIT_EXCEPTION_1D 0x5D
158#define SVM_EXIT_EXCEPTION_1E 0x5E
159#define SVM_EXIT_EXCEPTION_1F 0x5F
160/** Physical maskable interrupt. */
161#define SVM_EXIT_INTR 0x60
162/** Non-maskable interrupt. */
163#define SVM_EXIT_NMI 0x61
164/** System Management interrupt. */
165#define SVM_EXIT_SMI 0x62
166/** Physical INIT signal. */
167#define SVM_EXIT_INIT 0x63
168/** Virtual interrupt. */
169#define SVM_EXIT_VINTR 0x64
170/** Write to CR0 that changed any bits other than CR0.TS or CR0.MP. */
171#define SVM_EXIT_CR0_SEL_WRITE 0x65
172/** IDTR read. */
173#define SVM_EXIT_IDTR_READ 0x66
174/** GDTR read. */
175#define SVM_EXIT_GDTR_READ 0x67
176/** LDTR read. */
177#define SVM_EXIT_LDTR_READ 0x68
178/** TR read. */
179#define SVM_EXIT_TR_READ 0x69
180/** IDTR write. */
181#define SVM_EXIT_IDTR_WRITE 0x6A
182/** GDTR write. */
183#define SVM_EXIT_GDTR_WRITE 0x6B
184/** LDTR write. */
185#define SVM_EXIT_LDTR_WRITE 0x6C
186/** TR write. */
187#define SVM_EXIT_TR_WRITE 0x6D
188/** RDTSC instruction. */
189#define SVM_EXIT_RDTSC 0x6E
190/** RDPMC instruction. */
191#define SVM_EXIT_RDPMC 0x6F
192/** PUSHF instruction. */
193#define SVM_EXIT_PUSHF 0x70
194/** POPF instruction. */
195#define SVM_EXIT_POPF 0x71
196/** CPUID instruction. */
197#define SVM_EXIT_CPUID 0x72
198/** RSM instruction. */
199#define SVM_EXIT_RSM 0x73
200/** IRET instruction. */
201#define SVM_EXIT_IRET 0x74
202/** software interrupt (INTn instructions). */
203#define SVM_EXIT_SWINT 0x75
204/** INVD instruction. */
205#define SVM_EXIT_INVD 0x76
206/** PAUSE instruction. */
207#define SVM_EXIT_PAUSE 0x77
208/** HLT instruction. */
209#define SVM_EXIT_HLT 0x78
210/** INVLPG instructions. */
211#define SVM_EXIT_INVLPG 0x79
212/** INVLPGA instruction. */
213#define SVM_EXIT_INVLPGA 0x7A
214/** IN or OUT accessing protected port (the EXITINFO1 field provides more information). */
215#define SVM_EXIT_IOIO 0x7B
216/** RDMSR or WRMSR access to protected MSR. */
217#define SVM_EXIT_MSR 0x7C
218/** task switch. */
219#define SVM_EXIT_TASK_SWITCH 0x7D
220/** FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt. */
221#define SVM_EXIT_FERR_FREEZE 0x7E
222/** Shutdown. */
223#define SVM_EXIT_SHUTDOWN 0x7F
224/** VMRUN instruction. */
225#define SVM_EXIT_VMRUN 0x80
226/** VMMCALL instruction. */
227#define SVM_EXIT_VMMCALL 0x81
228/** VMLOAD instruction. */
229#define SVM_EXIT_VMLOAD 0x82
230/** VMSAVE instruction. */
231#define SVM_EXIT_VMSAVE 0x83
232/** STGI instruction. */
233#define SVM_EXIT_STGI 0x84
234/** CLGI instruction. */
235#define SVM_EXIT_CLGI 0x85
236/** SKINIT instruction. */
237#define SVM_EXIT_SKINIT 0x86
238/** RDTSCP instruction. */
239#define SVM_EXIT_RDTSCP 0x87
240/** ICEBP instruction. */
241#define SVM_EXIT_ICEBP 0x88
242/** WBINVD instruction. */
243#define SVM_EXIT_WBINVD 0x89
244/** MONITOR instruction. */
245#define SVM_EXIT_MONITOR 0x8A
246/** MWAIT instruction uncond. */
247#define SVM_EXIT_MWAIT_UNCOND 0x8B
248/** MWAIT instruction when armed. */
249#define SVM_EXIT_MWAIT_ARMED 0x8C
250/** Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault). */
251#define SVM_EXIT_NPF 0x400
252
253/** @} */
254
255
256/** @name SVM_VMCB.ctrl.u32InterceptCtrl1
257 * @{
258 */
259/** 0 Intercept INTR (physical maskable interrupt) */
260#define SVM_CTRL1_INTERCEPT_INTR RT_BIT(0)
261/** 1 Intercept NMI */
262#define SVM_CTRL1_INTERCEPT_NMI RT_BIT(1)
263/** 2 Intercept SMI */
264#define SVM_CTRL1_INTERCEPT_SMI RT_BIT(2)
265/** 3 Intercept INIT */
266#define SVM_CTRL1_INTERCEPT_INIT RT_BIT(3)
267/** 4 Intercept VINTR (virtual maskable interrupt) */
268#define SVM_CTRL1_INTERCEPT_VINTR RT_BIT(4)
269/** 5 Intercept CR0 writes that change bits other than CR0.TS or CR0.MP */
270#define SVM_CTRL1_INTERCEPT_CR0 RT_BIT(5)
271/** 6 Intercept reads of IDTR */
272#define SVM_CTRL1_INTERCEPT_IDTR_READS RT_BIT(6)
273/** 7 Intercept reads of GDTR */
274#define SVM_CTRL1_INTERCEPT_GDTR_READS RT_BIT(7)
275/** 8 Intercept reads of LDTR */
276#define SVM_CTRL1_INTERCEPT_LDTR_READS RT_BIT(8)
277/** 9 Intercept reads of TR */
278#define SVM_CTRL1_INTERCEPT_TR_READS RT_BIT(9)
279/** 10 Intercept writes of IDTR */
280#define SVM_CTRL1_INTERCEPT_IDTR_WRITES RT_BIT(10)
281/** 11 Intercept writes of GDTR */
282#define SVM_CTRL1_INTERCEPT_GDTR_WRITES RT_BIT(11)
283/** 12 Intercept writes of LDTR */
284#define SVM_CTRL1_INTERCEPT_LDTR_WRITES RT_BIT(12)
285/** 13 Intercept writes of TR */
286#define SVM_CTRL1_INTERCEPT_TR_WRITES RT_BIT(13)
287/** 14 Intercept RDTSC instruction */
288#define SVM_CTRL1_INTERCEPT_RDTSC RT_BIT(14)
289/** 15 Intercept RDPMC instruction */
290#define SVM_CTRL1_INTERCEPT_RDPMC RT_BIT(15)
291/** 16 Intercept PUSHF instruction */
292#define SVM_CTRL1_INTERCEPT_PUSHF RT_BIT(16)
293/** 17 Intercept POPF instruction */
294#define SVM_CTRL1_INTERCEPT_POPF RT_BIT(17)
295/** 18 Intercept CPUID instruction */
296#define SVM_CTRL1_INTERCEPT_CPUID RT_BIT(18)
297/** 19 Intercept RSM instruction */
298#define SVM_CTRL1_INTERCEPT_RSM RT_BIT(19)
299/** 20 Intercept IRET instruction */
300#define SVM_CTRL1_INTERCEPT_IRET RT_BIT(20)
301/** 21 Intercept INTn instruction */
302#define SVM_CTRL1_INTERCEPT_INTN RT_BIT(21)
303/** 22 Intercept INVD instruction */
304#define SVM_CTRL1_INTERCEPT_INVD RT_BIT(22)
305/** 23 Intercept PAUSE instruction */
306#define SVM_CTRL1_INTERCEPT_PAUSE RT_BIT(23)
307/** 24 Intercept HLT instruction */
308#define SVM_CTRL1_INTERCEPT_HLT RT_BIT(24)
309/** 25 Intercept INVLPG instruction */
310#define SVM_CTRL1_INTERCEPT_INVLPG RT_BIT(25)
311/** 26 Intercept INVLPGA instruction */
312#define SVM_CTRL1_INTERCEPT_INVLPGA RT_BIT(26)
313/** 27 IOIO_PROT Intercept IN/OUT accesses to selected ports. */
314#define SVM_CTRL1_INTERCEPT_INOUT_BITMAP RT_BIT(27)
315/** 28 MSR_PROT Intercept RDMSR or WRMSR accesses to selected MSRs. */
316#define SVM_CTRL1_INTERCEPT_MSR_SHADOW RT_BIT(28)
317/** 29 Intercept task switches. */
318#define SVM_CTRL1_INTERCEPT_TASK_SWITCH RT_BIT(29)
319/** 30 FERR_FREEZE: intercept processor "freezing" during legacy FERR handling. */
320#define SVM_CTRL1_INTERCEPT_FERR_FREEZE RT_BIT(30)
321/** 31 Intercept shutdown events. */
322#define SVM_CTRL1_INTERCEPT_SHUTDOWN RT_BIT(31)
323/** @} */
324
325
326/** @name SVM_VMCB.ctrl.u32InterceptCtrl2
327 * @{
328 */
329/** 0 Intercept VMRUN instruction */
330#define SVM_CTRL2_INTERCEPT_VMRUN RT_BIT(0)
331/** 1 Intercept VMMCALL instruction */
332#define SVM_CTRL2_INTERCEPT_VMMCALL RT_BIT(1)
333/** 2 Intercept VMLOAD instruction */
334#define SVM_CTRL2_INTERCEPT_VMLOAD RT_BIT(2)
335/** 3 Intercept VMSAVE instruction */
336#define SVM_CTRL2_INTERCEPT_VMSAVE RT_BIT(3)
337/** 4 Intercept STGI instruction */
338#define SVM_CTRL2_INTERCEPT_STGI RT_BIT(4)
339/** 5 Intercept CLGI instruction */
340#define SVM_CTRL2_INTERCEPT_CLGI RT_BIT(5)
341/** 6 Intercept SKINIT instruction */
342#define SVM_CTRL2_INTERCEPT_SKINIT RT_BIT(6)
343/** 7 Intercept RDTSCP instruction */
344#define SVM_CTRL2_INTERCEPT_RDTSCP RT_BIT(7)
345/** 8 Intercept ICEBP instruction */
346#define SVM_CTRL2_INTERCEPT_ICEBP RT_BIT(8)
347/** 9 Intercept WBINVD instruction */
348#define SVM_CTRL2_INTERCEPT_WBINVD RT_BIT(9)
349/** 10 Intercept MONITOR instruction */
350#define SVM_CTRL2_INTERCEPT_MONITOR RT_BIT(10)
351/** 11 Intercept MWAIT instruction unconditionally */
352#define SVM_CTRL2_INTERCEPT_MWAIT_UNCOND RT_BIT(11)
353/** 12 Intercept MWAIT instruction when armed */
354#define SVM_CTRL2_INTERCEPT_MWAIT_ARMED RT_BIT(12)
355/** @} */
356
357/** @name SVM_VMCB.ctrl.u64NestedPaging
358 * @{
359 */
360#define SVM_NESTED_PAGING_ENABLE RT_BIT(0)
361/** @} */
362
363/** @name SVM_VMCB.ctrl.u64IntShadow
364 * @{
365 */
366#define SVM_INTERRUPT_SHADOW_ACTIVE RT_BIT(0)
367/** @} */
368
369
370/** @name SVM_INTCTRL.u3Type
371 * @{
372 */
373/** External or virtual interrupt. */
374#define SVM_EVENT_EXTERNAL_IRQ 0
375/** Non-maskable interrupt. */
376#define SVM_EVENT_NMI 1
377/** Exception; fault or trap. */
378#define SVM_EVENT_EXCEPTION 3
379/** Software interrupt. */
380#define SVM_EVENT_SOFTWARE_INT 4
381/** @} */
382
383
384
385
386/**
387 * SVM Selector type; includes hidden parts
388 */
389#pragma pack(1)
390typedef struct
391{
392 uint16_t u16Sel;
393 uint16_t u16Attr;
394 uint32_t u32Limit;
395 uint64_t u64Base; /**< Only lower 32 bits are implemented for CS, DS, ES & SS. */
396} SVMSEL;
397#pragma pack()
398
399/**
400 * SVM GDTR/IDTR type
401 */
402#pragma pack(1)
403typedef struct
404{
405 uint16_t u16Reserved1;
406 uint16_t u16Reserved2;
407 uint32_t u32Limit; /**< Only lower 16 bits are implemented. */
408 uint64_t u64Base;
409} SVMGDTR;
410#pragma pack()
411
412typedef SVMGDTR SVMIDTR;
413
414/**
415 * SVM Event injection structure
416 */
417#pragma pack(1)
418typedef union
419{
420 struct
421 {
422 uint32_t u8Vector : 8;
423 uint32_t u3Type : 3;
424 uint32_t u1ErrorCodeValid : 1;
425 uint32_t u19Reserved : 19;
426 uint32_t u1Valid : 1;
427 uint32_t u32ErrorCode : 32;
428 } n;
429 uint64_t au64[1];
430} SVM_EVENT;
431#pragma pack()
432
433
434/**
435 * SVM Interrupt control structure
436 */
437#pragma pack(1)
438typedef union
439{
440 struct
441 {
442 uint32_t u8VTPR : 8;
443 uint32_t u1VIrqValid : 1;
444 uint32_t u7Reserved : 7;
445 uint32_t u4VIrqPriority : 4;
446 uint32_t u1IgnoreTPR : 1;
447 uint32_t u3Reserved : 3;
448 uint32_t u1VIrqMasking : 1;
449 uint32_t u7Reserved2 : 7;
450 uint32_t u8VIrqVector : 8;
451 uint32_t u24Reserved : 24;
452 } n;
453 uint64_t au64[1];
454} SVM_INTCTRL;
455#pragma pack()
456
457
458/**
459 * SVM TLB control structure
460 */
461#pragma pack(1)
462typedef union
463{
464 struct
465 {
466 uint32_t u32ASID : 32;
467 uint32_t u1TLBFlush : 1;
468 uint32_t u7Reserved : 7;
469 uint32_t u24Reserved : 24;
470 } n;
471 uint64_t au64[1];
472} SVM_TLBCTRL;
473#pragma pack()
474
475
476/**
477 * SVM IOIO exit structure
478 */
479#pragma pack(1)
480typedef union
481{
482 struct
483 {
484 uint32_t u1Type : 1; /**< 0 = out, 1 = in */
485 uint32_t u1Reserved : 1;
486 uint32_t u1STR : 1;
487 uint32_t u1REP : 1;
488 uint32_t u1OP8 : 1;
489 uint32_t u1OP16 : 1;
490 uint32_t u1OP32 : 1;
491 uint32_t u1ADDR16 : 1;
492 uint32_t u1ADDR32 : 1;
493 uint32_t u1ADDR64 : 1;
494 uint32_t u6Reserved : 6;
495 uint32_t u16Port : 16;
496 } n;
497 uint32_t au32[1];
498} SVM_IOIO_EXIT;
499#pragma pack()
500
501/**
502 * SVM nested paging structure
503 */
504#pragma pack(1)
505typedef union
506{
507 struct
508 {
509 uint32_t u1NestedPaging : 1; /**< enabled/disabled */
510 } n;
511 uint64_t au64[1];
512} SVM_NPCTRL;
513#pragma pack()
514
515/**
516 * SVM VM Control Block. (VMCB)
517 */
518#pragma pack(1)
519typedef struct _SVM_VMCB
520{
521 /** Control Area. */
522 struct
523 {
524 /** Offset 0x00 - Intercept reads of CR0-15. */
525 uint16_t u16InterceptRdCRx;
526 /** Offset 0x02 - Intercept writes to CR0-15. */
527 uint16_t u16InterceptWrCRx;
528 /** Offset 0x04 - Intercept reads of DR0-15. */
529 uint16_t u16InterceptRdDRx;
530 /** Offset 0x06 - Intercept writes to DR0-15. */
531 uint16_t u16InterceptWrDRx;
532 /** Offset 0x08 - Intercept exception vectors 0-31. */
533 uint32_t u32InterceptException;
534 /** Offset 0x0C - Intercept control field 1. */
535 uint32_t u32InterceptCtrl1;
536 /** Offset 0x0C - Intercept control field 2. */
537 uint32_t u32InterceptCtrl2;
538 /** Offset 0x14-0x3F - Reserved. */
539 uint8_t u8Reserved[0x40-0x14];
540 /** Offset 0x40 - Physical address of IOPM. */
541 uint64_t u64IOPMPhysAddr;
542 /** Offset 0x48 - Physical address of MSRPM. */
543 uint64_t u64MSRPMPhysAddr;
544 /** Offset 0x50 - TSC Offset. */
545 uint64_t u64TSCOffset;
546 /** Offset 0x58 - TLB control field. */
547 SVM_TLBCTRL TLBCtrl;
548 /** Offset 0x60 - Interrupt control field. */
549 SVM_INTCTRL IntCtrl;
550 /** Offset 0x68 - Interrupt shadow. */
551 uint64_t u64IntShadow;
552 /** Offset 0x70 - Exit code. */
553 uint64_t u64ExitCode;
554 /** Offset 0x78 - Exit info 1. */
555 uint64_t u64ExitInfo1;
556 /** Offset 0x80 - Exit info 2. */
557 uint64_t u64ExitInfo2;
558 /** Offset 0x88 - Exit Interrupt info. */
559 SVM_EVENT ExitIntInfo;
560 /** Offset 0x90 - Nested Paging. */
561 SVM_NPCTRL NestedPaging;
562 /** Offset 0x98-0xA7 - Reserved. */
563 uint8_t u8Reserved2[0xA8-0x98];
564 /** Offset 0xA8 - Event injection. */
565 SVM_EVENT EventInject;
566 /** Offset 0xB0 - Host CR3 for nested paging. */
567 uint64_t u64NestedPagingCR3;
568 /** Offset 0xB8 - LBR Virtualization. */
569 uint64_t u64LBRVirt;
570 } ctrl;
571
572 /** Offset 0xC0-0x3FF - Reserved. */
573 uint8_t u8Reserved3[0x400-0xC0];
574
575 /** State Save Area. Starts at offset 0x400. */
576 struct
577 {
578 /** Offset 0x400 - Guest ES register + hidden parts. */
579 SVMSEL ES;
580 /** Offset 0x410 - Guest CS register + hidden parts. */
581 SVMSEL CS;
582 /** Offset 0x420 - Guest SS register + hidden parts. */
583 SVMSEL SS;
584 /** Offset 0x430 - Guest DS register + hidden parts. */
585 SVMSEL DS;
586 /** Offset 0x440 - Guest FS register + hidden parts. */
587 SVMSEL FS;
588 /** Offset 0x450 - Guest GS register + hidden parts. */
589 SVMSEL GS;
590 /** Offset 0x460 - Guest GDTR register. */
591 SVMGDTR GDTR;
592 /** Offset 0x470 - Guest LDTR register + hidden parts. */
593 SVMSEL LDTR;
594 /** Offset 0x480 - Guest IDTR register. */
595 SVMIDTR IDTR;
596 /** Offset 0x490 - Guest TR register + hidden parts. */
597 SVMSEL TR;
598 /** Offset 0x4A0-0x4CA - Reserved. */
599 uint8_t u8Reserved4[0x4CB-0x4A0];
600 /** Offset 0x4CB - CPL. */
601 uint8_t u8CPL;
602 /** Offset 0x4CC-0x4CF - Reserved. */
603 uint8_t u8Reserved5[0x4D0-0x4CC];
604 /** Offset 0x4D0 - EFER. */
605 uint64_t u64EFER;
606 /** Offset 0x4D8-0x547 - Reserved. */
607 uint8_t u8Reserved6[0x548-0x4D8];
608 /** Offset 0x548 - CR4. */
609 uint64_t u64CR4;
610 /** Offset 0x550 - CR3. */
611 uint64_t u64CR3;
612 /** Offset 0x558 - CR0. */
613 uint64_t u64CR0;
614 /** Offset 0x560 - DR7. */
615 uint64_t u64DR7;
616 /** Offset 0x568 - DR6. */
617 uint64_t u64DR6;
618 /** Offset 0x570 - RFLAGS. */
619 uint64_t u64RFlags;
620 /** Offset 0x578 - RIP. */
621 uint64_t u64RIP;
622 /** Offset 0x580-0x5D7 - Reserved. */
623 uint8_t u8Reserved7[0x5D8-0x580];
624 /** Offset 0x5D8 - RSP. */
625 uint64_t u64RSP;
626 /** Offset 0x5E0-0x5F7 - Reserved. */
627 uint8_t u8Reserved8[0x5F8-0x5E0];
628 /** Offset 0x5F8 - RAX. */
629 uint64_t u64RAX;
630 /** Offset 0x600 - STAR. */
631 uint64_t u64STAR;
632 /** Offset 0x608 - LSTAR. */
633 uint64_t u64LSTAR;
634 /** Offset 0x610 - CSTAR. */
635 uint64_t u64CSTAR;
636 /** Offset 0x618 - SFMASK. */
637 uint64_t u64SFMASK;
638 /** Offset 0x620 - KernelGSBase. */
639 uint64_t u64KernelGSBase;
640 /** Offset 0x628 - SYSENTER_CS. */
641 uint64_t u64SysEnterCS;
642 /** Offset 0x630 - SYSENTER_ESP. */
643 uint64_t u64SysEnterESP;
644 /** Offset 0x638 - SYSENTER_EIP. */
645 uint64_t u64SysEnterEIP;
646 /** Offset 0x640 - CR2. */
647 uint64_t u64CR2;
648 /** Offset 0x648-0x667 - Reserved. */
649 uint8_t u8Reserved9[0x668-0x648];
650 /** Offset 0x668 - G_PAT. */
651 uint64_t u64GPAT;
652 /** Offset 0x670 - DBGCTL. */
653 uint64_t u64DBGCTL;
654 /** Offset 0x678 - BR_FROM. */
655 uint64_t u64BR_FROM;
656 /** Offset 0x680 - BR_TO. */
657 uint64_t u64BR_TO;
658 /** Offset 0x688 - LASTEXCPFROM. */
659 uint64_t u64LASTEXCPFROM;
660 /** Offset 0x690 - LASTEXCPTO. */
661 uint64_t u64LASTEXCPTO;
662 } guest;
663
664 /** Offset 0x698-0xFFF- Reserved. */
665 uint8_t u8Reserved10[0x1000-0x698];
666} SVM_VMCB;
667#pragma pack()
668
669
670/**
671 * Prepares for and executes VMRUN (32 bits guests).
672 *
673 * @returns VBox status code.
674 * @param pVMCBHostPhys Physical address of host VMCB.
675 * @param pVMCBPhys Physical address of the VMCB.
676 * @param pCtx Guest context.
677 */
678DECLASM(int) SVMVMRun(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
679
680/**
681 * Prepares for and executes VMRUN (64 bits guests).
682 *
683 * @returns VBox status code.
684 * @param pVMCBHostPhys Physical address of host VMCB.
685 * @param pVMCBPhys Physical address of the VMCB.
686 * @param pCtx Guest context.
687 */
688DECLASM(int) SVMVMRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx);
689
690/**
691 * Executes INVLPGA.
692 *
693 * @param pPageGC Virtual page to invalidate.
694 * @param u32ASID Tagged TLB id.
695 */
696DECLASM(void) SVMInvlpgA(RTGCPTR pPageGC, uint32_t u32ASID);
697
698#ifdef IN_RING0
699HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt);
700HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
701#endif /* IN_RING0 */
702
703/** @} */
704
705#endif
706
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette