[99485] | 1 | /** @file
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| 2 | * ARMv8 Generic Interrupt Controller Architecture v3 (GICv3) definitions.
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| 3 | */
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| 4 |
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| 5 | /*
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| 6 | * Copyright (C) 2023 Oracle and/or its affiliates.
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| 7 | *
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| 8 | * This file is part of VirtualBox base platform packages, as
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| 9 | * available from https://www.virtualbox.org.
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| 10 | *
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| 11 | * This program is free software; you can redistribute it and/or
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| 12 | * modify it under the terms of the GNU General Public License
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| 13 | * as published by the Free Software Foundation, in version 3 of the
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| 14 | * License.
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| 15 | *
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| 16 | * This program is distributed in the hope that it will be useful, but
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| 17 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 19 | * General Public License for more details.
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| 20 | *
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| 21 | * You should have received a copy of the GNU General Public License
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| 22 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 23 | *
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| 24 | * The contents of this file may alternatively be used under the terms
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| 25 | * of the Common Development and Distribution License Version 1.0
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| 26 | * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
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| 27 | * in the VirtualBox distribution, in which case the provisions of the
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| 28 | * CDDL are applicable instead of those of the GPL.
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| 29 | *
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| 30 | * You may elect to license modified versions of this file under the
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| 31 | * terms and conditions of either the GPL or the CDDL or both.
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| 32 | *
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| 33 | * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
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| 34 | */
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| 35 |
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| 36 | #ifndef VBOX_INCLUDED_gic_h
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| 37 | #define VBOX_INCLUDED_gic_h
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| 38 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 39 | # pragma once
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| 40 | #endif
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| 41 |
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| 42 | #include <iprt/types.h>
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| 43 | #include <iprt/armv8.h>
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| 44 |
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[99734] | 45 | /** @name INTIDs - Interrupt identifier ranges.
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| 46 | * @{ */
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| 47 | /** Start of the SGI (Software Generated Interrupts) range. */
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| 48 | #define GIC_INTID_RANGE_SGI_START 0
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| 49 | /** Last valid SGI (Software Generated Interrupts) identifier. */
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| 50 | #define GIC_INTID_RANGE_SGI_LAST 15
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[99485] | 51 |
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[99734] | 52 | /** Start of the PPI (Private Peripheral Interrupts) range. */
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| 53 | #define GIC_INTID_RANGE_PPI_START 16
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| 54 | /** Last valid PPI (Private Peripheral Interrupts) identifier. */
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| 55 | #define GIC_INTID_RANGE_PPI_LAST 31
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| 56 |
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| 57 | /** Start of the SPI (Shared Peripheral Interrupts) range. */
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| 58 | #define GIC_INTID_RANGE_SPI_START 32
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| 59 | /** Last valid SPI (Shared Peripheral Interrupts) identifier. */
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| 60 | #define GIC_INTID_RANGE_SPI_LAST 1019
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| 61 |
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| 62 | /** Start of the special interrupt range. */
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| 63 | #define GIC_INTID_RANGE_SPECIAL_START 1020
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| 64 | /** Last valid special interrupt identifier. */
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| 65 | #define GIC_INTID_RANGE_SPECIAL_LAST 1023
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| 66 | /** Value for an interrupt acknowledge if no pending interrupt with sufficient
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| 67 | * priority, security state or interrupt group. */
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| 68 | # define GIC_INTID_RANGE_SPECIAL_NO_INTERRUPT 1023
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| 69 |
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| 70 | /** Start of the extended PPI (Private Peripheral Interrupts) range. */
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| 71 | #define GIC_INTID_RANGE_EPPI_START 1056
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| 72 | /** Last valid extended PPI (Private Peripheral Interrupts) identifier. */
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| 73 | #define GIC_INTID_RANGE_EPPI_LAST 1119
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| 74 |
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| 75 | /** Start of the extended SPI (Shared Peripheral Interrupts) range. */
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| 76 | #define GIC_INTID_RANGE_ESPI_START 4096
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| 77 | /** Last valid extended SPI (Shared Peripheral Interrupts) identifier. */
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| 78 | #define GIC_INTID_RANGE_ESPI_LAST 5119
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| 79 |
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| 80 | /** Start of the LPI (Locality-specific Peripheral Interrupts) range. */
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| 81 | #define GIC_INTID_RANGE_LPI_START 8192
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| 82 | /** @} */
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| 83 |
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| 84 |
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[99485] | 85 | /** @name GICD - GIC Distributor registers.
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| 86 | * @{ */
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| 87 | /** Size of the distributor register frame. */
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| 88 | #define GIC_DIST_REG_FRAME_SIZE _64K
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[99578] | 89 |
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[99485] | 90 | /** Distributor Control Register - RW. */
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| 91 | #define GIC_DIST_REG_CTLR_OFF 0x0000
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[99578] | 92 | /** Bit 0 - Enable Group 0 interrupts. */
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| 93 | # define GIC_DIST_REG_CTRL_ENABLE_GRP0 RT_BIT_32(0)
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| 94 | # define GIC_DIST_REG_CTRL_ENABLE_GRP0_BIT 0
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| 95 | /** Bit 1 - Enable Non-secure Group 1 interrupts. */
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| 96 | # define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS RT_BIT_32(1)
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| 97 | # define GIC_DIST_REG_CTRL_ENABLE_GRP1_NS_BIT 1
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| 98 | /** Bit 2 - Enable Secure Group 1 interrupts. */
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| 99 | # define GIC_DIST_REG_CTRL_ENABLE_GRP1_S RT_BIT_32(2)
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| 100 | # define GIC_DIST_REG_CTRL_ENABLE_GRP1_S_BIT 2
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| 101 | /** Bit 4 - Affinity Routing Enable, Secure state. */
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| 102 | # define GIC_DIST_REG_CTRL_ARE_S RT_BIT_32(4)
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| 103 | # define GIC_DIST_REG_CTRL_ARE_S_BIT 4
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| 104 | /** Bit 5 - Affinity Routing Enable, Non-secure state. */
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| 105 | # define GIC_DIST_REG_CTRL_ARE_NS RT_BIT_32(5)
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| 106 | # define GIC_DIST_REG_CTRL_ARE_NS_BIT 5
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| 107 | /** Bit 6 - Disable Security. */
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| 108 | # define GIC_DIST_REG_CTRL_DS RT_BIT_32(6)
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| 109 | # define GIC_DIST_REG_CTRL_DS_BIT 6
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| 110 | /** Bit 7 - Enable 1 of N Wakeup Functionality. */
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| 111 | # define GIC_DIST_REG_CTRL_E1NWF RT_BIT_32(7)
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| 112 | # define GIC_DIST_REG_CTRL_E1NWF_BIT 7
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| 113 | /** Bit 31 - Register Write Pending. */
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| 114 | # define GIC_DIST_REG_CTRL_RWP RT_BIT_32(31)
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| 115 | # define GIC_DIST_REG_CTRL_RWP_BIT 31
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| 116 |
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[99485] | 117 | /** Interrupt Controller Type Register - RO. */
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| 118 | #define GIC_DIST_REG_TYPER_OFF 0x0004
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[99578] | 119 | /** Bit 0 - 4 - Maximum number of SPIs supported. */
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| 120 | # define GIC_DIST_REG_TYPER_NUM_ITLINES ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT(2) \
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| 121 | | RT_BIT_32(3) | RT_BIT_32(4))
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| 122 | # define GIC_DIST_REG_TYPER_NUM_ITLINES_SET(a_NumSpis) ((a_NumSpis) & GIC_DIST_REG_TYPER_NUM_ITLINES)
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| 123 | /** Bit 5 - 7 - Reports number of PEs that can be used when affinity routing is not enabled, minus 1. */
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| 124 | # define GIC_DIST_REG_TYPER_NUM_PES (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT(7))
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| 125 | # define GIC_DIST_REG_TYPER_NUM_PES_SET(a_Pes) (((a_Pes) << 5) & GIC_DIST_REG_TYPER_NUM_PES)
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| 126 | /** Bit 8 - Extended SPI range implemented. */
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| 127 | # define GIC_DIST_REG_TYPER_ESPI RT_BIT_32(8)
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| 128 | # define GIC_DIST_REG_TYPER_ESPI_BIT 8
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| 129 | /** Bit 9 - Non-maskable interrupt priority supported. */
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| 130 | # define GIC_DIST_REG_TYPER_NMI RT_BIT_32(9)
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| 131 | # define GIC_DIST_REG_TYPER_NMI_BIT 9
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| 132 | /** Bit 10 - Indicates whether the implementation supports two security states. */
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| 133 | # define GIC_DIST_REG_TYPER_SECURITY_EXTN RT_BIT_32(10)
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| 134 | # define GIC_DIST_REG_TYPER_SECURITY_EXTN_BIT 10
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| 135 | /** Bit 11 - 15 - The number of supported LPIs. */
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| 136 | # define GIC_DIST_REG_TYPER_NUM_LPIS ( RT_BIT_32(11) | RT_BIT_32(12) | RT_BIT(13) \
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| 137 | | RT_BIT_32(14) | RT_BIT_32(15))
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| 138 | # define GIC_DIST_REG_TYPER_NUM_LPIS_SET(a_Lpis) (((a_Lpis) << 11) & GIC_DIST_REG_TYPER_NUM_LPIS)
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| 139 | /** Bit 16 - Indicates whether the implementation supports message based interrupts by writing to Distributor registers. */
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| 140 | # define GIC_DIST_REG_TYPER_MBIS RT_BIT_32(16)
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| 141 | # define GIC_DIST_REG_TYPER_MBIS_BIT 16
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| 142 | /** Bit 17 - Indicates whether the implementation supports LPIs. */
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| 143 | # define GIC_DIST_REG_TYPER_LPIS RT_BIT_32(17)
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| 144 | # define GIC_DIST_REG_TYPER_LPIS_BIT 17
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| 145 | /** Bit 18 - Indicates whether the implementation supports Direct Virtual LPI injection (FEAT_GICv4). */
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| 146 | # define GIC_DIST_REG_TYPER_DVIS RT_BIT_32(18)
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| 147 | # define GIC_DIST_REG_TYPER_DVIS_BIT 18
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| 148 | /** Bit 19 - 23 - The number of interrupt identifer bits supported, minus one. */
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| 149 | # define GIC_DIST_REG_TYPER_IDBITS ( RT_BIT_32(19) | RT_BIT_32(20) | RT_BIT(21) \
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| 150 | | RT_BIT_32(22) | RT_BIT_32(23))
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| 151 | # define GIC_DIST_REG_TYPER_IDBITS_SET(a_Bits) (((a_Bits) << 19) & GIC_DIST_REG_TYPER_IDBITS)
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| 152 | /** Bit 24 - Affinity 3 valid. Indicates whether the Distributor supports nonzero values of Affinity level 3. */
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| 153 | # define GIC_DIST_REG_TYPER_A3V RT_BIT_32(24)
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| 154 | # define GIC_DIST_REG_TYPER_A3V_BIT 24
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| 155 | /** Bit 25 - Indicates whether 1 of N SPI interrupts are supported. */
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| 156 | # define GIC_DIST_REG_TYPER_NO1N RT_BIT_32(25)
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| 157 | # define GIC_DIST_REG_TYPER_NO1N_BIT 25
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| 158 | /** Bit 26 - Range Selector Support. */
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| 159 | # define GIC_DIST_REG_TYPER_RSS RT_BIT_32(26)
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| 160 | # define GIC_DIST_REG_TYPER_RSS_BIT 26
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| 161 | /** Bit 27 - 31 - Indicates maximum INTID in the Extended SPI range. */
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| 162 | # define GIC_DIST_REG_TYPER_ESPI_RANGE ( RT_BIT_32(27) | RT_BIT_32(28) | RT_BIT(29) \
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| 163 | | RT_BIT_32(30) | RT_BIT_32(31))
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| 164 | # define GIC_DIST_REG_TYPER_ESPI_RANGE_SET(a_Range) (((a_Range) << 27) & GIC_DIST_REG_TYPER_ESPI_RANGE)
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| 165 |
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[99485] | 166 | /** Distributor Implementer Identification Register - RO. */
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| 167 | #define GIC_DIST_REG_IIDR_OFF 0x0008
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| 168 | /** Interrupt Controller Type Register 2 - RO. */
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| 169 | #define GIC_DIST_REG_TYPER2_OFF 0x000c
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| 170 | /** Error Reporting Status Register (optional) - RW. */
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[99916] | 171 | #define GIC_DIST_REG_STATUSR_OFF 0x0010
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[99485] | 172 | /** Set SPI Register - WO. */
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| 173 | #define GIC_DIST_REG_SETSPI_NSR_OFF 0x0040
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| 174 | /** Clear SPI Register - WO. */
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| 175 | #define GIC_DIST_REG_CLRSPI_NSR_OFF 0x0048
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| 176 | /** Set SPI, Secure Register - WO. */
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| 177 | #define GIC_DIST_REG_SETSPI_SR_OFF 0x0050
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| 178 | /** Clear SPI, Secure Register - WO. */
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| 179 | #define GIC_DIST_REG_CLRSPI_SR_OFF 0x0058
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| 180 |
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| 181 | /** Interrupt Group Registers, start offset - RW. */
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| 182 | #define GIC_DIST_REG_IGROUPRn_OFF_START 0x0080
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| 183 | /** Interrupt Group Registers, last offset - RW. */
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| 184 | #define GIC_DIST_REG_IGROUPRn_OFF_LAST 0x00fc
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| 185 |
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| 186 | /** Interrupt Set Enable Registers, start offset - RW. */
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| 187 | #define GIC_DIST_REG_ISENABLERn_OFF_START 0x0100
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| 188 | /** Interrupt Set Enable Registers, last offset - RW. */
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| 189 | #define GIC_DIST_REG_ISENABLERn_OFF_LAST 0x017c
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| 190 | /** Interrupt Clear Enable Registers, start offset - RW. */
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| 191 | #define GIC_DIST_REG_ICENABLERn_OFF_START 0x0180
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| 192 | /** Interrupt Clear Enable Registers, last offset - RW. */
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| 193 | #define GIC_DIST_REG_ICENABLERn_OFF_LAST 0x01fc
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| 194 |
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| 195 | /** Interrupt Set Pending Registers, start offset - RW. */
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| 196 | #define GIC_DIST_REG_ISPENDRn_OFF_START 0x0200
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| 197 | /** Interrupt Set Pending Registers, last offset - RW. */
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| 198 | #define GIC_DIST_REG_ISPENDRn_OFF_LAST 0x027c
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| 199 | /** Interrupt Clear Pending Registers, start offset - RW. */
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| 200 | #define GIC_DIST_REG_ICPENDRn_OFF_START 0x0280
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| 201 | /** Interrupt Clear Pending Registers, last offset - RW. */
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| 202 | #define GIC_DIST_REG_ICPENDRn_OFF_LAST 0x02fc
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| 203 |
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| 204 | /** Interrupt Set Active Registers, start offset - RW. */
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| 205 | #define GIC_DIST_REG_ISACTIVERn_OFF_START 0x0300
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| 206 | /** Interrupt Set Active Registers, last offset - RW. */
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| 207 | #define GIC_DIST_REG_ISACTIVERn_OFF_LAST 0x037c
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| 208 | /** Interrupt Clear Active Registers, start offset - RW. */
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| 209 | #define GIC_DIST_REG_ICACTIVERn_OFF_START 0x0380
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| 210 | /** Interrupt Clear Active Registers, last offset - RW. */
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| 211 | #define GIC_DIST_REG_ICACTIVERn_OFF_LAST 0x03fc
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| 212 |
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| 213 | /** Interrupt Priority Registers, start offset - RW. */
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| 214 | #define GIC_DIST_REG_IPRIORITYn_OFF_START 0x0400
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| 215 | /** Interrupt Priority Registers, last offset - RW. */
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| 216 | #define GIC_DIST_REG_IPRIORITYn_OFF_LAST 0x07f8
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| 217 |
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| 218 | /** Interrupt Processor Targets Registers, start offset - RO/RW. */
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| 219 | #define GIC_DIST_REG_ITARGETSRn_OFF_START 0x0800
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| 220 | /** Interrupt Processor Targets Registers, last offset - RO/RW. */
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| 221 | #define GIC_DIST_REG_ITARGETSRn_OFF_LAST 0x0bf8
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| 222 |
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| 223 | /** Interrupt Configuration Registers, start offset - RW. */
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| 224 | #define GIC_DIST_REG_ICFGRn_OFF_START 0x0c00
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| 225 | /** Interrupt Configuration Registers, last offset - RW. */
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| 226 | #define GIC_DIST_REG_ICFGRn_OFF_LAST 0x0cfc
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| 227 |
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| 228 | /** Interrupt Group Modifier Registers, start offset - RW. */
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| 229 | #define GIC_DIST_REG_IGRPMODRn_OFF_START 0x0d00
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| 230 | /** Interrupt Group Modifier Registers, last offset - RW. */
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| 231 | #define GIC_DIST_REG_IGRPMODRn_OFF_LAST 0x0d7c
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| 232 |
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| 233 | /** Non-secure Access Control Registers, start offset - RW. */
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| 234 | #define GIC_DIST_REG_NSACRn_OFF_START 0x0e00
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| 235 | /** Non-secure Access Control Registers, last offset - RW. */
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| 236 | #define GIC_DIST_REG_NSACRn_OFF_LAST 0x0efc
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| 237 |
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| 238 | /** Software Generated Interrupt Register - RW. */
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| 239 | #define GIC_DIST_REG_SGIR_OFF 0x0f00
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| 240 |
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| 241 | /** SGI Clear Pending Registers, start offset - RW. */
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| 242 | #define GIC_DIST_REG_CPENDSGIRn_OFF_START 0x0f10
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| 243 | /** SGI Clear Pending Registers, last offset - RW. */
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| 244 | #define GIC_DIST_REG_CPENDSGIRn_OFF_LAST 0x0f1c
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| 245 | /** SGI Set Pending Registers, start offset - RW. */
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| 246 | #define GIC_DIST_REG_SPENDSGIRn_OFF_START 0x0f20
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| 247 | /** SGI Set Pending Registers, last offset - RW. */
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| 248 | #define GIC_DIST_REG_SPENDSGIRn_OFF_LAST 0x0f2c
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| 249 |
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| 250 | /** Non-maskable Interrupt Registers, start offset - RW. */
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| 251 | #define GIC_DIST_REG_INMIn_OFF_START 0x0f80
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| 252 | /** Non-maskable Interrupt Registers, last offset - RW. */
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| 253 | #define GIC_DIST_REG_INMIn_OFF_LAST 0x0ffc
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| 254 |
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| 255 |
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| 256 | /** Interrupt Group Registers for extended SPI range, start offset - RW. */
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| 257 | #define GIC_DIST_REG_IGROUPRnE_OFF_START 0x1000
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| 258 | /** Interrupt Group Registers for extended SPI range, last offset - RW. */
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| 259 | #define GIC_DIST_REG_IGROUPRnE_OFF_LAST 0x107c
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| 260 |
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| 261 | /** Interrupt Set Enable Registers for extended SPI range, start offset - RW. */
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| 262 | #define GIC_DIST_REG_ISENABLERnE_OFF_START 0x1200
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| 263 | /** Interrupt Set Enable Registers for extended SPI range, last offset - RW. */
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| 264 | #define GIC_DIST_REG_ISENABLERnE_OFF_LAST 0x127c
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| 265 | /** Interrupt Clear Enable Registers for extended SPI range, start offset - RW. */
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| 266 | #define GIC_DIST_REG_ICENABLERnE_OFF_START 0x1400
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| 267 | /** Interrupt Clear Enable Registers for extended SPI range, last offset - RW. */
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| 268 | #define GIC_DIST_REG_ICENABLERnE_OFF_LAST 0x147c
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| 269 |
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| 270 | /** Interrupt Set Pending Registers for extended SPI range, start offset - RW. */
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| 271 | #define GIC_DIST_REG_ISPENDRnE_OFF_START 0x1600
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| 272 | /** Interrupt Set Pending Registers for extended SPI range, last offset - RW. */
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| 273 | #define GIC_DIST_REG_ISPENDRnE_OFF_LAST 0x167c
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| 274 | /** Interrupt Clear Pending Registers for extended SPI range, start offset - RW. */
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| 275 | #define GIC_DIST_REG_ICPENDRnE_OFF_START 0x1800
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| 276 | /** Interrupt Clear Pending Registers for extended SPI range, last offset - RW. */
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| 277 | #define GIC_DIST_REG_ICPENDRnE_OFF_LAST 0x187c
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| 278 |
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| 279 | /** Interrupt Set Active Registers for extended SPI range, start offset - RW. */
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| 280 | #define GIC_DIST_REG_ISACTIVERnE_OFF_START 0x1a00
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| 281 | /** Interrupt Set Active Registers for extended SPI range, last offset - RW. */
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| 282 | #define GIC_DIST_REG_ISACTIVERnE_OFF_LAST 0x1a7c
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| 283 | /** Interrupt Clear Active Registers for extended SPI range, start offset - RW. */
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| 284 | #define GIC_DIST_REG_ICACTIVERnE_OFF_START 0x1c00
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| 285 | /** Interrupt Clear Active Registers for extended SPI range, last offset - RW. */
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| 286 | #define GIC_DIST_REG_ICACTIVERnE_OFF_LAST 0x1c7c
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| 287 |
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| 288 | /** Interrupt Priority Registers for extended SPI range, start offset - RW. */
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| 289 | #define GIC_DIST_REG_IPRIORITYnE_OFF_START 0x2000
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| 290 | /** Interrupt Priority Registers for extended SPI range, last offset - RW. */
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| 291 | #define GIC_DIST_REG_IPRIORITYnE_OFF_LAST 0x23fc
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| 292 |
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| 293 | /** Interrupt Configuration Registers for extended SPI range, start offset - RW. */
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| 294 | #define GIC_DIST_REG_ICFGRnE_OFF_START 0x3000
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| 295 | /** Interrupt Configuration Registers for extended SPI range, last offset - RW. */
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| 296 | #define GIC_DIST_REG_ICFGRnE_OFF_LAST 0x30fc
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| 297 |
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| 298 | /** Interrupt Group Modifier Registers for extended SPI range, start offset - RW. */
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| 299 | #define GIC_DIST_REG_IGRPMODRnE_OFF_START 0x3400
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| 300 | /** Interrupt Group Modifier Registers for extended SPI range, last offset - RW. */
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| 301 | #define GIC_DIST_REG_IGRPMODRnE_OFF_LAST 0x347c
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| 302 |
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| 303 | /** Non-secure Access Control Registers for extended SPI range, start offset - RW. */
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| 304 | #define GIC_DIST_REG_NSACRnE_OFF_START 0x3600
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| 305 | /** Non-secure Access Control Registers for extended SPI range, last offset - RW. */
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| 306 | #define GIC_DIST_REG_NSACRnE_OFF_LAST 0x367c
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| 307 |
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| 308 | /** Non-maskable Interrupt Registers for extended SPIs, start offset - RW. */
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| 309 | #define GIC_DIST_REG_INMInE_OFF_START 0x3b00
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| 310 | /** Non-maskable Interrupt Registers for extended SPIs, last offset - RW. */
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| 311 | #define GIC_DIST_REG_INMInE_OFF_LAST 0x3b7c
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| 312 |
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| 313 | /** Interrupt Routing Registers, start offset - RW. */
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| 314 | #define GIC_DIST_REG_IROUTERn_OFF_START 0x6100
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| 315 | /** Interrupt Routing Registers, last offset - RW. */
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| 316 | #define GIC_DIST_REG_IROUTERn_OFF_LAST 0x7fd8
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| 317 | /** Interrupt Routing Registers for extended SPI range, start offset - RW. */
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| 318 | #define GIC_DIST_REG_IROUTERnE_OFF_START 0x8000
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| 319 | /** Interrupt Routing Registers for extended SPI range, last offset - RW. */
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| 320 | #define GIC_DIST_REG_IROUTERnE_OFF_LAST 0x9ffc
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| 321 |
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| 322 | /** Distributor Peripheral ID2 Register - RO. */
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| 323 | #define GIC_DIST_REG_PIDR2_OFF 0xffe8
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[99578] | 324 | /** Bit 4 - 7 - GIC architecture revision */
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| 325 | # define GIC_DIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \
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| 326 | | RT_BIT_32(7))
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| 327 | # define GIC_DIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
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| 328 | /** GICv1 architecture revision. */
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| 329 | # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV1 0x1
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| 330 | /** GICv2 architecture revision. */
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| 331 | # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV2 0x2
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| 332 | /** GICv3 architecture revision. */
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| 333 | # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV3 0x3
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| 334 | /** GICv4 architecture revision. */
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| 335 | # define GIC_DIST_REG_PIDR2_ARCH_REV_GICV4 0x4
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[99485] | 336 | /** @} */
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| 337 |
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| 338 |
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| 339 | /** @name GICD - GIC Redistributor registers.
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| 340 | * @{ */
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| 341 | /** Size of the redistributor register frame. */
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| 342 | #define GIC_REDIST_REG_FRAME_SIZE _64K
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| 343 | /** Redistributor Control Register - RW. */
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| 344 | #define GIC_REDIST_REG_CTLR_OFF 0x0000
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| 345 | /** Implementer Identification Register - RO. */
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| 346 | #define GIC_REDIST_REG_IIDR_OFF 0x0004
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| 347 | /** Redistributor Type Register - RO. */
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| 348 | #define GIC_REDIST_REG_TYPER_OFF 0x0008
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| 349 | /** Redistributor Error Reporting Status Register (optional) - RW. */
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| 350 | #define GIC_REDIST_REG_STATUSR_OFF 0x0010
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| 351 | /** Redistributor Wake Register - RW. */
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| 352 | #define GIC_REDIST_REG_WAKER_OFF 0x0014
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| 353 | /** Redistributor Report maximum PARTID and PMG Register - RO. */
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| 354 | #define GIC_REDIST_REG_MPAMIDR_OFF 0x0018
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| 355 | /** Redistributor Set PARTID and PMG Register - RW. */
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| 356 | #define GIC_REDIST_REG_PARTIDR_OFF 0x001c
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| 357 | /** Redistributor Set LPI Pending Register - WO. */
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| 358 | #define GIC_REDIST_REG_SETLPIR_OFF 0x0040
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| 359 | /** Redistributor Clear LPI Pending Register - WO. */
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| 360 | #define GIC_REDIST_REG_CLRLPIR_OFF 0x0048
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| 361 | /** Redistributor Properties Base Address Register - RW. */
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| 362 | #define GIC_REDIST_REG_PROPBASER_OFF 0x0070
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| 363 | /** Redistributor LPI Pending Table Base Address Register - RW. */
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| 364 | #define GIC_REDIST_REG_PENDBASER_OFF 0x0078
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| 365 | /** Redistributor Invalidate LPI Register - WO. */
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| 366 | #define GIC_REDIST_REG_INVLPIR_OFF 0x00a0
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| 367 | /** Redistributor Invalidate All Register - WO. */
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| 368 | #define GIC_REDIST_REG_INVALLR_OFF 0x00b0
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| 369 | /** Redistributor Synchronize Register - RO. */
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| 370 | #define GIC_REDIST_REG_SYNCR_OFF 0x00c0
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| 371 |
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| 372 | /** Redistributor Peripheral ID2 Register - RO. */
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| 373 | #define GIC_REDIST_REG_PIDR2_OFF 0xffe8
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[99578] | 374 | /** Bit 4 - 7 - GIC architecture revision */
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| 375 | # define GIC_REDIST_REG_PIDR2_ARCH_REV ( RT_BIT_32(4) | RT_BIT_32(5) | RT_BIT_32(6) \
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| 376 | | RT_BIT_32(7))
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| 377 | # define GIC_REDIST_REG_PIDR2_ARCH_REV_SET(a_ArchRev) (((a_ArchRev) << 4) & GIC_DIST_REG_PIDR2_ARCH_REV)
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| 378 | /** GICv1 architecture revision. */
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| 379 | # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV1 0x1
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| 380 | /** GICv2 architecture revision. */
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| 381 | # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV2 0x2
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| 382 | /** GICv3 architecture revision. */
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| 383 | # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3 0x3
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| 384 | /** GICv4 architecture revision. */
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| 385 | # define GIC_REDIST_REG_PIDR2_ARCH_REV_GICV4 0x4
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[99485] | 386 | /** @} */
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| 387 |
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| 388 |
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| 389 | /** @name GICD - GIC SGI and PPI Redistributor registers (Adjacent to the GIC Redistributor register space).
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| 390 | * @{ */
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| 391 | /** Size of the SGI and PPI redistributor register frame. */
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| 392 | #define GIC_REDIST_SGI_PPI_REG_FRAME_SIZE _64K
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| 393 |
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| 394 | /** Interrupt Group Register 0 - RW. */
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| 395 | #define GIC_REDIST_SGI_PPI_REG_IGROUPR0_OFF 0x0080
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| 396 | /** Interrupt Group Register 1 for extended PPI range - RW. */
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| 397 | #define GIC_REDIST_SGI_PPI_REG_IGROUPR1E_OFF 0x0084
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| 398 | /** Interrupt Group Register 2 for extended PPI range - RW. */
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| 399 | #define GIC_REDIST_SGI_PPI_REG_IGROUPR2E_OFF 0x0084
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| 400 |
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| 401 | /** Interrupt Set Enable Register 0 - RW. */
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| 402 | #define GIC_REDIST_SGI_PPI_REG_ISENABLER0_OFF 0x0100
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| 403 | /** Interrupt Set Enable Register 1 for extended PPI range - RW. */
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| 404 | #define GIC_REDIST_SGI_PPI_REG_ISENABLER1E_OFF 0x0104
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| 405 | /** Interrupt Set Enable Register 2 for extended PPI range - RW. */
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| 406 | #define GIC_REDIST_SGI_PPI_REG_ISENABLER2E_OFF 0x0108
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| 407 |
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| 408 | /** Interrupt Clear Enable Register 0 - RW. */
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[99734] | 409 | #define GIC_REDIST_SGI_PPI_REG_ICENABLER0_OFF 0x0180
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[99485] | 410 | /** Interrupt Clear Enable Register 1 for extended PPI range - RW. */
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[99734] | 411 | #define GIC_REDIST_SGI_PPI_REG_ICENABLER1E_OFF 0x0184
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[99485] | 412 | /** Interrupt Clear Enable Register 2 for extended PPI range - RW. */
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[99734] | 413 | #define GIC_REDIST_SGI_PPI_REG_ICENABLER2E_OFF 0x0188
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[99485] | 414 |
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| 415 | /** Interrupt Set Pend Register 0 - RW. */
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| 416 | #define GIC_REDIST_SGI_PPI_REG_ISPENDR0_OFF 0x0200
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| 417 | /** Interrupt Set Pend Register 1 for extended PPI range - RW. */
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| 418 | #define GIC_REDIST_SGI_PPI_REG_ISPENDR1E_OFF 0x0204
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| 419 | /** Interrupt Set Pend Register 2 for extended PPI range - RW. */
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| 420 | #define GIC_REDIST_SGI_PPI_REG_ISPENDR2E_OFF 0x0208
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| 421 |
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| 422 | /** Interrupt Clear Pend Register 0 - RW. */
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| 423 | #define GIC_REDIST_SGI_PPI_REG_ICPENDR0_OFF 0x0280
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| 424 | /** Interrupt Clear Pend Register 1 for extended PPI range - RW. */
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| 425 | #define GIC_REDIST_SGI_PPI_REG_ICPENDR1E_OFF 0x0284
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| 426 | /** Interrupt Clear Pend Register 2 for extended PPI range - RW. */
|
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| 427 | #define GIC_REDIST_SGI_PPI_REG_ICPENDR2E_OFF 0x0288
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| 428 |
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| 429 | /** Interrupt Set Active Register 0 - RW. */
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| 430 | #define GIC_REDIST_SGI_PPI_REG_ISACTIVER0_OFF 0x0300
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| 431 | /** Interrupt Set Active Register 1 for extended PPI range - RW. */
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| 432 | #define GIC_REDIST_SGI_PPI_REG_ISACTIVER1E_OFF 0x0304
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| 433 | /** Interrupt Set Active Register 2 for extended PPI range - RW. */
|
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| 434 | #define GIC_REDIST_SGI_PPI_REG_ISACTIVER2E_OFF 0x0308
|
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| 435 |
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| 436 | /** Interrupt Clear Active Register 0 - RW. */
|
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| 437 | #define GIC_REDIST_SGI_PPI_REG_ICACTIVER0_OFF 0x0380
|
---|
| 438 | /** Interrupt Clear Active Register 1 for extended PPI range - RW. */
|
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| 439 | #define GIC_REDIST_SGI_PPI_REG_ICACTIVER1E_OFF 0x0384
|
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| 440 | /** Interrupt Clear Active Register 2 for extended PPI range - RW. */
|
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| 441 | #define GIC_REDIST_SGI_PPI_REG_ICACTIVER2E_OFF 0x0388
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| 442 |
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| 443 | /** Interrupt Priority Registers, start offset - RW. */
|
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| 444 | #define GIC_REDIST_SGI_PPI_REG_IPRIORITYn_OFF_START 0x0400
|
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| 445 | /** Interrupt Priority Registers, last offset - RW. */
|
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| 446 | #define GIC_REDIST_SGI_PPI_REG_IPRIORITYn_OFF_LAST 0x041c
|
---|
| 447 | /** Interrupt Priority Registers for extended PPI range, start offset - RW. */
|
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| 448 | #define GIC_REDIST_SGI_PPI_REG_IPRIORITYnE_OFF_START 0x0420
|
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| 449 | /** Interrupt Priority Registers for extended PPI range, last offset - RW. */
|
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| 450 | #define GIC_REDIST_SGI_PPI_REG_IPRIORITYnE_OFF_LAST 0x045c
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| 451 |
|
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| 452 | /** SGI Configuration Register - RW. */
|
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| 453 | #define GIC_REDIST_SGI_PPI_REG_ICFGR0_OFF 0x0c00
|
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| 454 | /** PPI Configuration Register - RW. */
|
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| 455 | #define GIC_REDIST_SGI_PPI_REG_ICFGR1_OFF 0x0c04
|
---|
| 456 | /** Extended PPI Configuration Register, start offset - RW. */
|
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| 457 | #define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_START 0x0c08
|
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| 458 | /** Extended PPI Configuration Register, last offset - RW. */
|
---|
| 459 | #define GIC_REDIST_SGI_PPI_REG_ICFGRnE_OFF_LAST 0x0c14
|
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| 460 |
|
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| 461 | /** Interrupt Group Modifier Register 0 - RW. */
|
---|
| 462 | #define GIC_REDIST_SGI_PPI_REG_IGRPMODR0_OFF 0x0d00
|
---|
| 463 | /** Interrupt Group Modifier Register 1 for extended PPI range - RW. */
|
---|
| 464 | #define GIC_REDIST_SGI_PPI_REG_IGRPMODR1E_OFF 0x0d04
|
---|
| 465 | /** Interrupt Group Modifier Register 2 for extended PPI range - RW. */
|
---|
| 466 | #define GIC_REDIST_SGI_PPI_REG_IGRPMODR2E_OFF 0x0d08
|
---|
| 467 |
|
---|
| 468 | /** Non Secure Access Control Register - RW. */
|
---|
| 469 | #define GIC_REDIST_SGI_PPI_REG_NSACR_OFF 0x0e00
|
---|
| 470 |
|
---|
| 471 | /** Non maskable Interrupt Register for PPIs - RW. */
|
---|
| 472 | #define GIC_REDIST_SGI_PPI_REG_INMIR0_OFF 0x0f80
|
---|
| 473 | /** Non maskable Interrupt Register for Extended PPIs, start offset - RW. */
|
---|
| 474 | #define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_START 0x0f84
|
---|
| 475 | /** Non maskable Interrupt Register for Extended PPIs, last offset - RW. */
|
---|
| 476 | #define GIC_REDIST_SGI_PPI_REG_INMIRnE_OFF_LAST 0x0ffc
|
---|
| 477 | /** @} */
|
---|
| 478 |
|
---|
| 479 |
|
---|
| 480 | #endif /* !VBOX_INCLUDED_gic_h */
|
---|
| 481 |
|
---|