VirtualBox

source: vbox/trunk/include/VBox/em.h@ 27023

Last change on this file since 27023 was 26855, checked in by vboxsync, 15 years ago

Introduced EMInterpretInstructionCPUEx to allow user-level instruction emulation.
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  • Property svn:keywords set to Author Date Id Revision
File size: 11.5 KB
Line 
1/** @file
2 * EM - Execution Monitor. (VMM)
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_em_h
31#define ___VBox_em_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/trpm.h>
36#include <VBox/dis.h>
37
38RT_C_DECLS_BEGIN
39
40/** @defgroup grp_em The Execution Monitor / Manager API
41 * @{
42 */
43
44/** Enable to allow V86 code to run in raw mode. */
45#define VBOX_RAW_V86
46
47/**
48 * The Execution Manager State.
49 */
50typedef enum EMSTATE
51{
52 /** Not yet started. */
53 EMSTATE_NONE = 1,
54 /** Raw-mode execution. */
55 EMSTATE_RAW,
56 /** Hardware accelerated raw-mode execution. */
57 EMSTATE_HWACC,
58 /** PARAV function. */
59 EMSTATE_PARAV,
60 /** Recompiled mode execution. */
61 EMSTATE_REM,
62 /** Execution is halted. (waiting for interrupt) */
63 EMSTATE_HALTED,
64 /** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
65 EMSTATE_WAIT_SIPI,
66 /** Execution is suspended. */
67 EMSTATE_SUSPENDED,
68 /** The VM is terminating. */
69 EMSTATE_TERMINATING,
70 /** Guest debug event from raw-mode is being processed. */
71 EMSTATE_DEBUG_GUEST_RAW,
72 /** Guest debug event from hardware accelerated mode is being processed. */
73 EMSTATE_DEBUG_GUEST_HWACC,
74 /** Guest debug event from recompiled-mode is being processed. */
75 EMSTATE_DEBUG_GUEST_REM,
76 /** Hypervisor debug event being processed. */
77 EMSTATE_DEBUG_HYPER,
78 /** The VM has encountered a fatal error. (And everyone is panicing....) */
79 EMSTATE_GURU_MEDITATION,
80 /** Just a hack to ensure that we get a 32-bit integer. */
81 EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
82} EMSTATE;
83
84
85/**
86 * EMInterpretInstructionCPUEx execution modes.
87 */
88typedef enum
89{
90 /** Only supervisor code (CPL=0). */
91 EMCODETYPE_SUPERVISOR,
92 /** User-level code only. */
93 EMCODETYPE_USER,
94 /** Supervisor and user-level code (use with great care!). */
95 EMCODETYPE_ALL,
96 /** Just a hack to ensure that we get a 32-bit integer. */
97 EMCODETYPE_32BIT_HACK = 0x7fffffff
98} EMCODETYPE;
99
100VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu);
101VMMDECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
102
103/** @name Callback handlers for instruction emulation functions.
104 * These are placed here because IOM wants to use them as well.
105 * @{
106 */
107typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
108typedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
109typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
110typedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
111typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
112typedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
113typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
114typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
115typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
116typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
117/** @} */
118
119
120/**
121 * Checks if raw ring-3 execute mode is enabled.
122 *
123 * @returns true if enabled.
124 * @returns false if disabled.
125 * @param pVM The VM to operate on.
126 */
127#define EMIsRawRing3Enabled(pVM) ((pVM)->fRawR3Enabled)
128
129/**
130 * Checks if raw ring-0 execute mode is enabled.
131 *
132 * @returns true if enabled.
133 * @returns false if disabled.
134 * @param pVM The VM to operate on.
135 */
136#define EMIsRawRing0Enabled(pVM) ((pVM)->fRawR0Enabled)
137
138VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
139VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
140VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
141VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
142 PDISCPUSTATE pDISState, unsigned *pcbInstr);
143VMMDECL(int) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
144VMMDECL(int) EMInterpretInstructionCPUEx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType);
145VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
146VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
147VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
148VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
149VMMDECL(int) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
150VMMDECL(int) EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
151VMMDECL(int) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
152VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
153VMMDECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
154VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
155VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
156VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
157VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
158VMMDECL(VBOXSTRICTRC) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
159VMMDECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
160VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
161
162/* Wrap EMInterpretInstructionCPUEx for supervisor code only interpretation.
163 */
164inline int EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
165{
166 return EMInterpretInstructionCPUEx(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMCODETYPE_SUPERVISOR);
167}
168
169/** @name Assembly routines
170 * @{ */
171VMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
172VMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
173VMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
174VMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
175VMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
176VMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
177VMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
178VMMDECL(int) EMEmulateLockXor(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
179VMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
180VMMDECL(int) EMEmulateLockAnd(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
181VMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
182VMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
183VMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
184VMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
185VMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
186VMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
187VMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
188VMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
189VMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
190VMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
191/** @} */
192
193/** @name REM locking routines
194 * @{ */
195VMMDECL(void) EMRemUnlock(PVM pVM);
196VMMDECL(void) EMRemLock(PVM pVM);
197VMMDECL(bool) EMRemIsLockOwner(PVM pVM);
198VMMDECL(int) EMTryEnterRemLock(PVM pVM);
199/** @} */
200
201#ifdef IN_RING3
202/** @defgroup grp_em_r3 The EM Host Context Ring-3 API
203 * @ingroup grp_em
204 * @{
205 */
206VMMR3DECL(int) EMR3Init(PVM pVM);
207VMMR3DECL(int) EMR3InitCPU(PVM pVM);
208VMMR3DECL(void) EMR3Relocate(PVM pVM);
209VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu);
210VMMR3DECL(void) EMR3Reset(PVM pVM);
211VMMR3DECL(int) EMR3Term(PVM pVM);
212VMMR3DECL(int) EMR3TermCPU(PVM pVM);
213VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
214VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
215VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
216VMMR3DECL(int) EMR3Interpret(PVM pVM);
217
218VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM);
219
220/**
221 * Command argument for EMR3RawSetMode().
222 *
223 * It's possible to extend this interface to change several
224 * execution modes at once should the need arise.
225 */
226typedef enum EMRAWMODE
227{
228 /** No raw execution. */
229 EMRAW_NONE = 0,
230 /** Enable Only ring-3 raw execution. */
231 EMRAW_RING3_ENABLE,
232 /** Only ring-3 raw execution. */
233 EMRAW_RING3_DISABLE,
234 /** Enable raw ring-0 execution. */
235 EMRAW_RING0_ENABLE,
236 /** Disable raw ring-0 execution. */
237 EMRAW_RING0_DISABLE,
238 EMRAW_END
239} EMRAWMODE;
240
241VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode);
242/** @} */
243#endif /* IN_RING3 */
244
245
246#ifdef IN_RC
247/** @defgroup grp_em_gc The EM Guest Context API
248 * @ingroup grp_em
249 * @{
250 */
251VMMRCDECL(int) EMGCTrap(PVM pVM, unsigned uTrap, PCPUMCTXCORE pRegFrame);
252VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
253VMMRCDECL(uint32_t) EMGCEmulateCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
254VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
255VMMRCDECL(uint32_t) EMGCEmulateCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
256VMMRCDECL(uint32_t) EMGCEmulateLockXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
257VMMRCDECL(uint32_t) EMGCEmulateXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
258/** @} */
259#endif /* IN_RC */
260
261/** @} */
262
263RT_C_DECLS_END
264
265#endif
266
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