1 | /** @file
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2 | * EM - Execution Monitor. (VMM)
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License (GPL) as published by the Free Software
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12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | *
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16 | * The contents of this file may alternatively be used under the terms
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17 | * of the Common Development and Distribution License Version 1.0
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18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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19 | * VirtualBox OSE distribution, in which case the provisions of the
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20 | * CDDL are applicable instead of those of the GPL.
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21 | *
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22 | * You may elect to license modified versions of this file under the
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23 | * terms and conditions of either the GPL or the CDDL or both.
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24 | *
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25 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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26 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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27 | * additional information or have any questions.
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28 | */
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29 |
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30 | #ifndef ___VBox_em_h
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31 | #define ___VBox_em_h
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32 |
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33 | #include <VBox/cdefs.h>
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34 | #include <VBox/types.h>
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35 | #include <VBox/trpm.h>
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36 | #include <VBox/dis.h>
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37 |
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38 | RT_C_DECLS_BEGIN
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39 |
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40 | /** @defgroup grp_em The Execution Monitor / Manager API
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41 | * @{
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42 | */
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43 |
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44 | /** Enable to allow V86 code to run in raw mode. */
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45 | #define VBOX_RAW_V86
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46 |
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47 | /**
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48 | * The Execution Manager State.
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49 | */
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50 | typedef enum EMSTATE
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51 | {
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52 | /** Not yet started. */
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53 | EMSTATE_NONE = 1,
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54 | /** Raw-mode execution. */
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55 | EMSTATE_RAW,
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56 | /** Hardware accelerated raw-mode execution. */
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57 | EMSTATE_HWACC,
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58 | /** PARAV function. */
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59 | EMSTATE_PARAV,
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60 | /** Recompiled mode execution. */
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61 | EMSTATE_REM,
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62 | /** Execution is halted. (waiting for interrupt) */
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63 | EMSTATE_HALTED,
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64 | /** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
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65 | EMSTATE_WAIT_SIPI,
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66 | /** Execution is suspended. */
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67 | EMSTATE_SUSPENDED,
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68 | /** The VM is terminating. */
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69 | EMSTATE_TERMINATING,
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70 | /** Guest debug event from raw-mode is being processed. */
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71 | EMSTATE_DEBUG_GUEST_RAW,
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72 | /** Guest debug event from hardware accelerated mode is being processed. */
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73 | EMSTATE_DEBUG_GUEST_HWACC,
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74 | /** Guest debug event from recompiled-mode is being processed. */
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75 | EMSTATE_DEBUG_GUEST_REM,
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76 | /** Hypervisor debug event being processed. */
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77 | EMSTATE_DEBUG_HYPER,
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78 | /** The VM has encountered a fatal error. (And everyone is panicing....) */
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79 | EMSTATE_GURU_MEDITATION,
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80 | /** Just a hack to ensure that we get a 32-bit integer. */
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81 | EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
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82 | } EMSTATE;
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83 |
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84 |
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85 | /**
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86 | * EMInterpretInstructionCPUEx execution modes.
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87 | */
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88 | typedef enum
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89 | {
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90 | /** Only supervisor code (CPL=0). */
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91 | EMCODETYPE_SUPERVISOR,
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92 | /** User-level code only. */
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93 | EMCODETYPE_USER,
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94 | /** Supervisor and user-level code (use with great care!). */
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95 | EMCODETYPE_ALL,
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96 | /** Just a hack to ensure that we get a 32-bit integer. */
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97 | EMCODETYPE_32BIT_HACK = 0x7fffffff
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98 | } EMCODETYPE;
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99 |
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100 | VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu);
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101 | VMMDECL(void) EMSetState(PVMCPU pVCpu, EMSTATE enmNewState);
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102 |
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103 | /** @name Callback handlers for instruction emulation functions.
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104 | * These are placed here because IOM wants to use them as well.
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105 | * @{
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106 | */
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107 | typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
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108 | typedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
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109 | typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
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110 | typedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
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111 | typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
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112 | typedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
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113 | typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
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114 | typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
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115 | typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
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116 | typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
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117 | /** @} */
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118 |
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119 |
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120 | /**
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121 | * Checks if raw ring-3 execute mode is enabled.
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122 | *
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123 | * @returns true if enabled.
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124 | * @returns false if disabled.
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125 | * @param pVM The VM to operate on.
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126 | */
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127 | #define EMIsRawRing3Enabled(pVM) ((pVM)->fRawR3Enabled)
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128 |
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129 | /**
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130 | * Checks if raw ring-0 execute mode is enabled.
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131 | *
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132 | * @returns true if enabled.
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133 | * @returns false if disabled.
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134 | * @param pVM The VM to operate on.
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135 | */
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136 | #define EMIsRawRing0Enabled(pVM) ((pVM)->fRawR0Enabled)
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137 |
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138 | VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
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139 | VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
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140 | VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
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141 | VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
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142 | PDISCPUSTATE pDISState, unsigned *pcbInstr);
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143 | VMMDECL(int) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
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144 | VMMDECL(int) EMInterpretInstructionCPUEx(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize, EMCODETYPE enmCodeType);
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145 | VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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146 | VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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147 | VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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148 | VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
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149 | VMMDECL(int) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
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150 | VMMDECL(int) EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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151 | VMMDECL(int) EMInterpretMWait(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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152 | VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
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153 | VMMDECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
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154 | VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
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155 | VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
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156 | VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
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157 | VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
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158 | VMMDECL(VBOXSTRICTRC) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
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159 | VMMDECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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160 | VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
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161 |
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162 | /* Wrap EMInterpretInstructionCPUEx for supervisor code only interpretation.
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163 | */
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164 | inline int EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
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165 | {
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166 | return EMInterpretInstructionCPUEx(pVM, pVCpu, pDISState, pRegFrame, pvFault, pcbSize, EMCODETYPE_SUPERVISOR);
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167 | }
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168 |
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169 | /** @name Assembly routines
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170 | * @{ */
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171 | VMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
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172 | VMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
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173 | VMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
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174 | VMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
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175 | VMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
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176 | VMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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177 | VMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
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178 | VMMDECL(int) EMEmulateLockXor(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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179 | VMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
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180 | VMMDECL(int) EMEmulateLockAnd(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
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181 | VMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
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182 | VMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
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183 | VMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
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184 | VMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
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185 | VMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
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186 | VMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
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187 | VMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
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188 | VMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
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189 | VMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
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190 | VMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
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191 | /** @} */
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192 |
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193 | /** @name REM locking routines
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194 | * @{ */
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195 | VMMDECL(void) EMRemUnlock(PVM pVM);
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196 | VMMDECL(void) EMRemLock(PVM pVM);
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197 | VMMDECL(bool) EMRemIsLockOwner(PVM pVM);
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198 | VMMDECL(int) EMTryEnterRemLock(PVM pVM);
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199 | /** @} */
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200 |
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201 | #ifdef IN_RING3
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202 | /** @defgroup grp_em_r3 The EM Host Context Ring-3 API
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203 | * @ingroup grp_em
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204 | * @{
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205 | */
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206 | VMMR3DECL(int) EMR3Init(PVM pVM);
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207 | VMMR3DECL(int) EMR3InitCPU(PVM pVM);
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208 | VMMR3DECL(void) EMR3Relocate(PVM pVM);
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209 | VMMR3DECL(void) EMR3ResetCpu(PVMCPU pVCpu);
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210 | VMMR3DECL(void) EMR3Reset(PVM pVM);
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211 | VMMR3DECL(int) EMR3Term(PVM pVM);
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212 | VMMR3DECL(int) EMR3TermCPU(PVM pVM);
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213 | VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
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214 | VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
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215 | VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
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216 | VMMR3DECL(int) EMR3Interpret(PVM pVM);
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217 |
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218 | VMMR3DECL(void) EMR3ReleaseOwnedLocks(PVM pVM);
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219 |
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220 | /**
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221 | * Command argument for EMR3RawSetMode().
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222 | *
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223 | * It's possible to extend this interface to change several
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224 | * execution modes at once should the need arise.
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225 | */
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226 | typedef enum EMRAWMODE
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227 | {
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228 | /** No raw execution. */
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229 | EMRAW_NONE = 0,
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230 | /** Enable Only ring-3 raw execution. */
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231 | EMRAW_RING3_ENABLE,
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232 | /** Only ring-3 raw execution. */
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233 | EMRAW_RING3_DISABLE,
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234 | /** Enable raw ring-0 execution. */
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235 | EMRAW_RING0_ENABLE,
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236 | /** Disable raw ring-0 execution. */
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237 | EMRAW_RING0_DISABLE,
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238 | EMRAW_END
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239 | } EMRAWMODE;
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240 |
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241 | VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode);
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242 | /** @} */
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243 | #endif /* IN_RING3 */
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244 |
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245 |
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246 | #ifdef IN_RC
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247 | /** @defgroup grp_em_gc The EM Guest Context API
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248 | * @ingroup grp_em
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249 | * @{
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250 | */
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251 | VMMRCDECL(int) EMGCTrap(PVM pVM, unsigned uTrap, PCPUMCTXCORE pRegFrame);
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252 | VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
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253 | VMMRCDECL(uint32_t) EMGCEmulateCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
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254 | VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
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255 | VMMRCDECL(uint32_t) EMGCEmulateCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
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256 | VMMRCDECL(uint32_t) EMGCEmulateLockXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
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257 | VMMRCDECL(uint32_t) EMGCEmulateXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
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258 | /** @} */
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259 | #endif /* IN_RC */
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260 |
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261 | /** @} */
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262 |
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263 | RT_C_DECLS_END
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264 |
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265 | #endif
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266 |
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