VirtualBox

source: vbox/trunk/include/VBox/em.h@ 19449

Last change on this file since 19449 was 19425, checked in by vboxsync, 16 years ago

Introduced EMSTATE_WAIT_SIPI VCPU state
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File size: 10.0 KB
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1/** @file
2 * EM - Execution Monitor.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_em_h
31#define ___VBox_em_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/trpm.h>
36#include <VBox/dis.h>
37
38__BEGIN_DECLS
39
40/** @defgroup grp_em The Execution Monitor / Manager API
41 * @{
42 */
43
44/** Enable to allow V86 code to run in raw mode. */
45#define VBOX_RAW_V86
46
47/**
48 * The Execution Manager State.
49 */
50typedef enum EMSTATE
51{
52 /** Not yet started. */
53 EMSTATE_NONE = 1,
54 /** Raw-mode execution. */
55 EMSTATE_RAW,
56 /** Hardware accelerated raw-mode execution. */
57 EMSTATE_HWACC,
58 /** PARAV function. */
59 EMSTATE_PARAV,
60 /** Recompiled mode execution. */
61 EMSTATE_REM,
62 /** Execution is halted. (waiting for interrupt) */
63 EMSTATE_HALTED,
64 /** Application processor execution is halted. (waiting for startup IPI (SIPI)) */
65 EMSTATE_WAIT_SIPI,
66 /** Execution is suspended. */
67 EMSTATE_SUSPENDED,
68 /** The VM is terminating. */
69 EMSTATE_TERMINATING,
70 /** Guest debug event from raw-mode is being processed. */
71 EMSTATE_DEBUG_GUEST_RAW,
72 /** Guest debug event from hardware accelerated mode is being processed. */
73 EMSTATE_DEBUG_GUEST_HWACC,
74 /** Guest debug event from recompiled-mode is being processed. */
75 EMSTATE_DEBUG_GUEST_REM,
76 /** Hypervisor debug event being processed. */
77 EMSTATE_DEBUG_HYPER,
78 /** The VM has encountered a fatal error. (And everyone is panicing....) */
79 EMSTATE_GURU_MEDITATION,
80 /** Just a hack to ensure that we get a 32-bit integer. */
81 EMSTATE_MAKE_32BIT_HACK = 0x7fffffff
82} EMSTATE;
83
84VMMDECL(EMSTATE) EMGetState(PVMCPU pVCpu);
85
86/** @name Callback handlers for instruction emulation functions.
87 * These are placed here because IOM wants to use them as well.
88 * @{
89 */
90typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2UINT32(void *pvParam1, uint64_t val2);
91typedef FNEMULATEPARAM2UINT32 *PFNEMULATEPARAM2UINT32;
92typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM2(void *pvParam1, size_t val2);
93typedef FNEMULATEPARAM2 *PFNEMULATEPARAM2;
94typedef DECLCALLBACK(uint32_t) FNEMULATEPARAM3(void *pvParam1, uint64_t val2, size_t val3);
95typedef FNEMULATEPARAM3 *PFNEMULATEPARAM3;
96typedef DECLCALLBACK(int) FNEMULATELOCKPARAM2(void *pvParam1, uint64_t val2, RTGCUINTREG32 *pf);
97typedef FNEMULATELOCKPARAM2 *PFNEMULATELOCKPARAM2;
98typedef DECLCALLBACK(int) FNEMULATELOCKPARAM3(void *pvParam1, uint64_t val2, size_t cb, RTGCUINTREG32 *pf);
99typedef FNEMULATELOCKPARAM3 *PFNEMULATELOCKPARAM3;
100/** @} */
101
102
103/**
104 * Checks if raw ring-3 execute mode is enabled.
105 *
106 * @returns true if enabled.
107 * @returns false if disabled.
108 * @param pVM The VM to operate on.
109 */
110#define EMIsRawRing3Enabled(pVM) ((pVM)->fRawR3Enabled)
111
112/**
113 * Checks if raw ring-0 execute mode is enabled.
114 *
115 * @returns true if enabled.
116 * @returns false if disabled.
117 * @param pVM The VM to operate on.
118 */
119#define EMIsRawRing0Enabled(pVM) ((pVM)->fRawR0Enabled)
120
121VMMDECL(void) EMSetInhibitInterruptsPC(PVMCPU pVCpu, RTGCUINTPTR PC);
122VMMDECL(RTGCUINTPTR) EMGetInhibitInterruptsPC(PVMCPU pVCpu);
123VMMDECL(int) EMInterpretDisasOne(PVM pVM, PVMCPU pVCpu, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr);
124VMMDECL(int) EMInterpretDisasOneEx(PVM pVM, PVMCPU pVCpu, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore,
125 PDISCPUSTATE pDISState, unsigned *pcbInstr);
126VMMDECL(int) EMInterpretInstruction(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
127VMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PVMCPU pVCpu, PDISCPUSTATE pDISState, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
128VMMDECL(int) EMInterpretCpuId(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
129VMMDECL(int) EMInterpretRdtsc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
130VMMDECL(int) EMInterpretRdpmc(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
131VMMDECL(int) EMInterpretRdtscp(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
132VMMDECL(int) EMInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC);
133VMMDECL(int) EMInterpretIret(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
134VMMDECL(int) EMInterpretDRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
135VMMDECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
136VMMDECL(int) EMInterpretCRxWrite(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen);
137VMMDECL(int) EMInterpretCRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx);
138VMMDECL(int) EMInterpretLMSW(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint16_t u16Data);
139VMMDECL(int) EMInterpretCLTS(PVM pVM, PVMCPU pVCpu);
140VMMDECL(int) EMInterpretPortIO(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp);
141VMMDECL(int) EMInterpretRdmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
142VMMDECL(int) EMInterpretWrmsr(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
143
144/** @name Assembly routines
145 * @{ */
146VMMDECL(uint32_t) EMEmulateCmp(uint32_t u32Param1, uint64_t u64Param2, size_t cb);
147VMMDECL(uint32_t) EMEmulateAnd(void *pvParam1, uint64_t u64Param2, size_t cb);
148VMMDECL(uint32_t) EMEmulateInc(void *pvParam1, size_t cb);
149VMMDECL(uint32_t) EMEmulateDec(void *pvParam1, size_t cb);
150VMMDECL(uint32_t) EMEmulateOr(void *pvParam1, uint64_t u64Param2, size_t cb);
151VMMDECL(int) EMEmulateLockOr(void *pvParam1, uint64_t u64Param2, size_t cbSize, RTGCUINTREG32 *pf);
152VMMDECL(uint32_t) EMEmulateXor(void *pvParam1, uint64_t u64Param2, size_t cb);
153VMMDECL(uint32_t) EMEmulateAdd(void *pvParam1, uint64_t u64Param2, size_t cb);
154VMMDECL(uint32_t) EMEmulateSub(void *pvParam1, uint64_t u64Param2, size_t cb);
155VMMDECL(uint32_t) EMEmulateAdcWithCarrySet(void *pvParam1, uint64_t u64Param2, size_t cb);
156VMMDECL(uint32_t) EMEmulateBtr(void *pvParam1, uint64_t u64Param2);
157VMMDECL(int) EMEmulateLockBtr(void *pvParam1, uint64_t u64Param2, RTGCUINTREG32 *pf);
158VMMDECL(uint32_t) EMEmulateBts(void *pvParam1, uint64_t u64Param2);
159VMMDECL(uint32_t) EMEmulateBtc(void *pvParam1, uint64_t u64Param2);
160VMMDECL(uint32_t) EMEmulateCmpXchg(void *pvParam1, uint64_t *pu32Param2, uint64_t u32Param3, size_t cbSize);
161VMMDECL(uint32_t) EMEmulateLockCmpXchg(void *pvParam1, uint64_t *pu64Param2, uint64_t u64Param3, size_t cbSize);
162VMMDECL(uint32_t) EMEmulateCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
163VMMDECL(uint32_t) EMEmulateLockCmpXchg8b(void *pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX);
164/** @} */
165
166#ifdef IN_RING3
167/** @defgroup grp_em_r3 The EM Host Context Ring-3 API
168 * @ingroup grp_em
169 * @{
170 */
171VMMR3DECL(int) EMR3Init(PVM pVM);
172VMMR3DECL(int) EMR3InitCPU(PVM pVM);
173VMMR3DECL(void) EMR3Relocate(PVM pVM);
174VMMR3DECL(void) EMR3Reset(PVM pVM);
175VMMR3DECL(int) EMR3Term(PVM pVM);
176VMMR3DECL(int) EMR3TermCPU(PVM pVM);
177VMMR3DECL(DECLNORETURN(void)) EMR3FatalError(PVMCPU pVCpu, int rc);
178VMMR3DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu);
179VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu);
180VMMR3DECL(int) EMR3Interpret(PVM pVM);
181
182/**
183 * Command argument for EMR3RawSetMode().
184 *
185 * It's possible to extend this interface to change several
186 * execution modes at once should the need arise.
187 */
188typedef enum EMRAWMODE
189{
190 /** No raw execution. */
191 EMRAW_NONE = 0,
192 /** Enable Only ring-3 raw execution. */
193 EMRAW_RING3_ENABLE,
194 /** Only ring-3 raw execution. */
195 EMRAW_RING3_DISABLE,
196 /** Enable raw ring-0 execution. */
197 EMRAW_RING0_ENABLE,
198 /** Disable raw ring-0 execution. */
199 EMRAW_RING0_DISABLE,
200 EMRAW_END
201} EMRAWMODE;
202
203VMMR3DECL(int) EMR3RawSetMode(PVM pVM, EMRAWMODE enmMode);
204/** @} */
205#endif /* IN_RING3 */
206
207
208#ifdef IN_RC
209/** @defgroup grp_em_gc The EM Guest Context API
210 * @ingroup grp_em
211 * @{
212 */
213VMMRCDECL(int) EMGCTrap(PVM pVM, unsigned uTrap, PCPUMCTXCORE pRegFrame);
214VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
215VMMRCDECL(uint32_t) EMGCEmulateCmpXchg(RTRCPTR pu32Param1, uint32_t *pu32Param2, uint32_t u32Param3, size_t cbSize, uint32_t *pEflags);
216VMMRCDECL(uint32_t) EMGCEmulateLockCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
217VMMRCDECL(uint32_t) EMGCEmulateCmpXchg8b(RTRCPTR pu32Param1, uint32_t *pEAX, uint32_t *pEDX, uint32_t uEBX, uint32_t uECX, uint32_t *pEflags);
218VMMRCDECL(uint32_t) EMGCEmulateLockXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
219VMMRCDECL(uint32_t) EMGCEmulateXAdd(RTRCPTR pu32Param1, uint32_t *pu32Param2, size_t cbSize, uint32_t *pEflags);
220/** @} */
221#endif /* IN_RC */
222
223/** @} */
224
225__END_DECLS
226
227#endif
228
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