disopcode.h@ 98264

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1	/** @file
2	* Disassembler - Opcodes
3	*/
4
5	/*
6	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
7	*
8	* This file is part of VirtualBox base platform packages, as
9	* available from https://www.virtualbox.org.
10	*
11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License
13	* as published by the Free Software Foundation, in version 3 of the
14	* License.
15	*
16	* This program is distributed in the hope that it will be useful, but
17	* WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19	* General Public License for more details.
20	*
21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, see <https://www.gnu.org/licenses>.
23	*
24	* The contents of this file may alternatively be used under the terms
25	* of the Common Development and Distribution License Version 1.0
26	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27	* in the VirtualBox distribution, in which case the provisions of the
28	* CDDL are applicable instead of those of the GPL.
29	*
30	* You may elect to license modified versions of this file under the
31	* terms and conditions of either the GPL or the CDDL or both.
32	*
33	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34	*/
35
36	#ifndef VBOX_INCLUDED_disopcode_h
37	#define VBOX_INCLUDED_disopcode_h
38	#ifndef RT_WITHOUT_PRAGMA_ONCE
39	# pragma once
40	#endif
41
42	#include <iprt/assert.h>
43
44	#define MODRM_MOD(a) (a>>6)
45	#define MODRM_REG(a) ((a>>3)&0x7)
46	#define MODRM_RM(a) (a&0x7)
47	#define MAKE_MODRM(mod, reg, rm) (((mod&3) << 6) \| ((reg&7) << 3) \| (rm&7))
48
49	#define SIB_SCALE(a) (a>>6)
50	#define SIB_INDEX(a) ((a>>3)&0x7)
51	#define SIB_BASE(a) (a&0x7)
52
53
54	/** @defgroup grp_dis_opcodes Opcodes (DISOPCODE::uOpCode)
55	* @ingroup grp_dis
56	* @{
57	*/
58	enum OPCODES
59	{
60	/** @name Full Intel X86 opcode list
61	* @{ */
62	OP_INVALID = 0,
63	OP_OPSIZE,
64	OP_ADDRSIZE,
65	OP_SEG,
66	OP_REPNE,
67	OP_REPE,
68	OP_REX,
69	OP_LOCK,
70	#ifndef IN_SLICKEDIT
71	OP_LAST_PREFIX = OP_LOCK, /*< Last prefix for disassembler. /
72	#else
73	OP_LAST_PREFIX = 7, /*< Last prefix for disassembler. /
74	#endif
75	OP_AND,
76	OP_OR,
77	OP_DAA,
78	OP_SUB,
79	OP_DAS,
80	OP_XOR,
81	OP_AAA,
82	OP_CMP,
83	OP_IMM_GRP1,
84	OP_AAS,
85	OP_INC,
86	OP_DEC,
87	OP_PUSHA,
88	OP_POPA,
89	OP_BOUND,
90	OP_ARPL,
91	OP_PUSH,
92	OP_POP,
93	OP_IMUL,
94	OP_INSB,
95	OP_INSWD,
96	OP_OUTSB,
97	OP_OUTSWD,
98	OP_JO,
99	OP_JNO,
100	OP_JC,
101	OP_JNC,
102	OP_JE,
103	OP_JNE,
104	OP_JBE,
105	OP_JNBE,
106	OP_JS,
107	OP_JNS,
108	OP_JP,
109	OP_JNP,
110	OP_JL,
111	OP_JNL,
112	OP_JLE,
113	OP_JNLE,
114	OP_ADD,
115	OP_TEST,
116	OP_XCHG,
117	OP_MOV,
118	OP_LEA,
119	OP_NOP,
120	OP_CBW,
121	OP_CWD,
122	OP_CALL,
123	OP_WAIT,
124	OP_PUSHF,
125	OP_POPF,
126	OP_SAHF,
127	OP_LAHF,
128	OP_MOVSB,
129	OP_MOVSWD,
130	OP_CMPSB,
131	OP_CMPWD,
132	OP_STOSB,
133	OP_STOSWD,
134	OP_LODSB,
135	OP_LODSWD,
136	OP_SCASB,
137	OP_SCASWD,
138	OP_SHIFT_GRP2,
139	OP_RETN,
140	OP_LES,
141	OP_LDS,
142	OP_ENTER,
143	OP_LEAVE,
144	OP_RETF,
145	OP_INT1,
146	OP_INT3,
147	OP_INT,
148	OP_INTO,
149	OP_IRET,
150	OP_AAM,
151	OP_AAD,
152	OP_SALC,
153	OP_XLAT,
154	OP_ESCF0,
155	OP_ESCF1,
156	OP_ESCF2,
157	OP_ESCF3,
158	OP_ESCF4,
159	OP_ESCF5,
160	OP_ESCF6,
161	OP_ESCF7,
162	OP_LOOPNE,
163	OP_LOOPE,
164	OP_LOOP,
165	OP_JECXZ,
166	OP_IN,
167	OP_OUT,
168	OP_JMP,
169	OP_2B_ESC,
170	OP_ADC,
171	OP_SBB,
172	OP_HLT,
173	OP_CMC,
174	OP_UNARY_GRP3,
175	OP_CLC,
176	OP_STC,
177	OP_CLI,
178	OP_STI,
179	OP_CLD,
180	OP_STD,
181	OP_INC_GRP4,
182	OP_IND_GRP5,
183	OP_GRP6,
184	OP_GRP7,
185	OP_LAR,
186	OP_LSL,
187	OP_SYSCALL,
188	OP_CLTS,
189	OP_SYSRET,
190	OP_INVD,
191	OP_WBINVD,
192	OP_ILLUD2,
193	OP_FEMMS,
194	OP_3DNOW,
195	OP_MOVUPS,
196	OP_MOVLPS,
197	OP_MOVHLPS = OP_MOVLPS, /*< @todo OP_MOVHLPS /
198	OP_UNPCKLPS,
199	OP_MOVHPS,
200	OP_MOVLHPS = OP_MOVHPS, /*< @todo OP_MOVLHPS /
201	OP_UNPCKHPS,
202	OP_PREFETCH_GRP16,
203	OP_MOV_CR,
204	OP_MOVAPS,
205	OP_CVTPI2PS,
206	OP_MOVNTPS,
207	OP_CVTTPS2PI,
208	OP_CVTPS2PI,
209	OP_UCOMISS,
210	OP_COMISS,
211	OP_WRMSR,
212	OP_RDTSC,
213	OP_RDTSCP,
214	OP_RDMSR,
215	OP_RDPMC,
216	OP_SYSENTER,
217	OP_SYSEXIT,
218	OP_GETSEC,
219	OP_PAUSE,
220	OP_CMOVO,
221	OP_CMOVNO,
222	OP_CMOVC,
223	OP_CMOVNC,
224	OP_CMOVZ,
225	OP_CMOVNZ,
226	OP_CMOVBE,
227	OP_CMOVNBE,
228	OP_CMOVS,
229	OP_CMOVNS,
230	OP_CMOVP,
231	OP_CMOVNP,
232	OP_CMOVL,
233	OP_CMOVNL,
234	OP_CMOVLE,
235	OP_CMOVNLE,
236	OP_MOVMSKPS,
237	OP_SQRTPS,
238	OP_RSQRTPS,
239	OP_RCPPS,
240	OP_ANDPS,
241	OP_ANDNPS,
242	OP_ORPS,
243	OP_XORPS,
244	OP_ADDPS,
245	OP_MULPS,
246	OP_CVTPS2PD,
247	OP_CVTDQ2PS,
248	OP_SUBPS,
249	OP_MINPS,
250	OP_DIVPS,
251	OP_MAXPS,
252	OP_PUNPCKLBW,
253	OP_PUNPCKLWD,
254	OP_PUNPCKLDQ,
255	OP_PACKSSWB,
256	OP_PCMPGTB,
257	OP_PCMPGTW,
258	OP_PCMPGTD,
259	OP_PCMPGTQ,
260	OP_PACKUSWB,
261	OP_PUNPCKHBW,
262	OP_PUNPCKHWD,
263	OP_PUNPCKHDQ,
264	OP_PACKSSDW,
265	OP_MOVD,
266	OP_MOVQ,
267	OP_PSHUFW,
268	OP_3B_ESC4,
269	OP_3B_ESC5,
270	OP_PCMPEQB,
271	OP_PCMPEQW,
272	OP_PCMPEQD,
273	OP_PCMPEQQ,
274	OP_SETO,
275	OP_SETNO,
276	OP_SETC,
277	OP_SETNC,
278	OP_SETE,
279	OP_SETNE,
280	OP_SETBE,
281	OP_SETNBE,
282	OP_SETS,
283	OP_SETNS,
284	OP_SETP,
285	OP_SETNP,
286	OP_SETL,
287	OP_SETNL,
288	OP_SETLE,
289	OP_SETNLE,
290	OP_CPUID,
291	OP_BT,
292	OP_SHLD,
293	OP_RSM,
294	OP_BTS,
295	OP_SHRD,
296	OP_GRP15,
297	OP_CMPXCHG,
298	OP_LSS,
299	OP_BTR,
300	OP_LFS,
301	OP_LGS,
302	OP_MOVZX,
303	OP_GRP10_INV,
304	OP_GRP8,
305	OP_BTC,
306	OP_BSF,
307	OP_BSR,
308	OP_MOVSX,
309	OP_XADD,
310	OP_CMPPS,
311	OP_MOVNTI,
312	OP_PINSRW,
313	OP_PEXTRW,
314	OP_SHUFPS,
315	OP_GRP9,
316	OP_BSWAP,
317	OP_ADDSUBPS,
318	OP_ADDSUBPD,
319	OP_PSRLW,
320	OP_PSRLD,
321	OP_PSRLQ,
322	OP_PADDQ,
323	OP_PMULLW,
324	OP_PMOVMSKB,
325	OP_PSUBUSB,
326	OP_PSUBUSW,
327	OP_PMINUB,
328	OP_PAND,
329	OP_PADDUSB,
330	OP_PADDUSW,
331	OP_PMAXUB,
332	OP_PANDN,
333	OP_PAVGB,
334	OP_PSRAW,
335	OP_PSRAD,
336	OP_PAVGW,
337	OP_PMULHUW,
338	OP_PMULHW,
339	OP_MOVNTQ,
340	OP_PSUBSB,
341	OP_PSUBSW,
342	OP_PMINSW,
343	OP_POR,
344	OP_PADDSB,
345	OP_PADDSW,
346	OP_PMAXSW,
347	OP_PXOR,
348	OP_LDDQU,
349	OP_PSLLW,
350	OP_PSLLD,
351	OP_PSSQ,
352	OP_PMULUDQ,
353	OP_PMADDWD,
354	OP_PSADBW,
355	OP_MASKMOVQ,
356	OP_PSUBB,
357	OP_PSUBW,
358	OP_PSUBD,
359	OP_PSUBQ,
360	OP_PADDB,
361	OP_PADDW,
362	OP_PADDD,
363	OP_MOVUPD,
364	OP_MOVLPD,
365	OP_UNPCKLPD,
366	OP_UNPCKHPD,
367	OP_MOVHPD,
368	OP_MOVAPD,
369	OP_CVTPI2PD,
370	OP_MOVNTPD,
371	OP_CVTTPD2PI,
372	OP_CVTPD2PI,
373	OP_UCOMISD,
374	OP_COMISD,
375	OP_MOVMSKPD,
376	OP_SQRTPD,
377	OP_ANDPD,
378	OP_ANDNPD,
379	OP_ORPD,
380	OP_XORPD,
381	OP_ADDPD,
382	OP_MULPD,
383	OP_CVTPD2PS,
384	OP_CVTPS2DQ,
385	OP_SUBPD,
386	OP_MINPD,
387	OP_DIVPD,
388	OP_MAXPD,
389	OP_GRP12,
390	OP_GRP13,
391	OP_GRP14,
392	OP_GRP17,
393	OP_EMMS,
394	OP_MMX_UD78,
395	OP_MMX_UD79,
396	OP_MMX_UD7A,
397	OP_MMX_UD7B,
398	OP_MMX_UD7C,
399	OP_MMX_UD7D,
400	OP_PUNPCKLQDQ,
401	OP_PUNPCKHQDQ,
402	OP_MOVDQA,
403	OP_PSHUFD,
404	OP_CMPPD,
405	OP_SHUFPD,
406	OP_CVTTPD2DQ,
407	OP_MOVNTDQ,
408	OP_MOVNTDQA,
409	OP_PACKUSDW,
410	OP_PSHUFB,
411	OP_PHADDW,
412	OP_PHADDD,
413	OP_PHADDSW,
414	OP_HADDPS,
415	OP_HADDPD,
416	OP_PMADDUBSW,
417	OP_PHSUBW,
418	OP_PHSUBD,
419	OP_PHSUBSW,
420	OP_HSUBPS,
421	OP_HSUBPD,
422	OP_PSIGNB,
423	OP_PSIGNW,
424	OP_PSIGND,
425	OP_PMULHRSW,
426	OP_PERMILPS,
427	OP_PERMILPD,
428	OP_TESTPS,
429	OP_TESTPD,
430	OP_PBLENDVB,
431	OP_CVTPH2PS,
432	OP_BLENDVPS,
433	OP_BLENDVPD,
434	OP_PERMPS,
435	OP_PERMD,
436	OP_PTEST,
437	OP_BROADCASTSS,
438	OP_BROADCASTSD,
439	OP_BROADCASTF128,
440	OP_PABSB,
441	OP_PABSW,
442	OP_PABSD,
443	OP_PMOVSXBW,
444	OP_PMOVSXBD,
445	OP_PMOVSXBQ,
446	OP_PMOVSXWD,
447	OP_PMOVSXWQ,
448	OP_PMOVSXDQ,
449	OP_PMOVZXBW,
450	OP_PMOVZXBD,
451	OP_PMOVZXBQ,
452	OP_PMOVZXWD,
453	OP_PMOVZXWQ,
454	OP_PMOVZXDQ,
455	OP_PMULDQ,
456	OP_PMINSB,
457	OP_PMINSD,
458	OP_PMINUW,
459	OP_PMINUD,
460	OP_PMAXSB,
461	OP_PMAXSD,
462	OP_PMAXUW,
463	OP_PMAXUD,
464	OP_PMULLD,
465	OP_PHMINPOSUW,
466	OP_PSRLVD,
467	OP_PSRAVD,
468	OP_PSLLVD,
469	OP_PBROADCASTD,
470	OP_PBROADCASTQ,
471	OP_PBROADCASTI128,
472	OP_PBROADCASTB,
473	OP_PBROADCASTW,
474	OP_PMASKMOVD,
475	OP_GATHER,
476	OP_FMADDSUB132PS,
477	OP_FMSUBADD132PS,
478	OP_FMADD132PS,
479	OP_FMADD132SS,
480	OP_FMSUB132PS,
481	OP_FMSUB132SS,
482	OP_FNMADD132PS,
483	OP_FNMADD132SS,
484	OP_FNMSUB132PS,
485	OP_FNMSUB132SS,
486	OP_FMADDSUB213PS,
487	OP_FMSUBADD213PS,
488	OP_FMADD213PS,
489	OP_FMADD213SS,
490	OP_FMSUB213PS,
491	OP_FMSUB213SS,
492	OP_FNMADD213PS,
493	OP_FNMADD213SS,
494	OP_FNMSUB213PS,
495	OP_FNMSUB213SS,
496	OP_FMADDSUB231PS,
497	OP_FMSUBADD231PS,
498	OP_FMADD231PS,
499	OP_FMADD231SS,
500	OP_FMSUB231PS,
501	OP_FMSUB231SS,
502	OP_FNMADD231PS,
503	OP_FNMADD231SS,
504	OP_FNMSUB231PS,
505	OP_FNMSUB231SS,
506	OP_AESIMC,
507	OP_AESENC,
508	OP_AESENCLAST,
509	OP_AESDEC,
510	OP_AESDECLAST,
511	OP_MOVBEGM,
512	OP_MOVBEMG,
513	OP_CRC32,
514	OP_POPCNT,
515	OP_TZCNT,
516	OP_LZCNT,
517	OP_ADCX,
518	OP_ADOX,
519	OP_ANDN,
520	OP_BZHI,
521	OP_BEXTR,
522	OP_BLSR,
523	OP_BLSMSK,
524	OP_BLSI,
525	OP_PEXT,
526	OP_PDEP,
527	OP_SHLX,
528	OP_SHRX,
529	OP_SARX,
530	OP_MULX,
531	OP_MASKMOVDQU,
532	OP_MASKMOVPS,
533	OP_MASKMOVPD,
534	OP_MOVSD,
535	OP_CVTSI2SD,
536	OP_CVTTSD2SI,
537	OP_CVTSD2SI,
538	OP_SQRTSD,
539	OP_ADDSD,
540	OP_MULSD,
541	OP_CVTSD2SS,
542	OP_SUBSD,
543	OP_MINSD,
544	OP_DIVSD,
545	OP_MAXSD,
546	OP_PSHUFLW,
547	OP_CMPSD,
548	OP_MOVDQ2Q,
549	OP_CVTPD2DQ,
550	OP_MOVSS,
551	OP_MOVSLDUP,
552	OP_MOVDDUP,
553	OP_MOVSHDUP,
554	OP_CVTSI2SS,
555	OP_CVTTSS2SI,
556	OP_CVTSS2SI,
557	OP_CVTSS2SD,
558	OP_SQRTSS,
559	OP_RSQRTSS,
560	OP_RCPSS,
561	OP_ADDSS,
562	OP_MULSS,
563	OP_CVTTPS2DQ,
564	OP_SUBSS,
565	OP_MINSS,
566	OP_DIVSS,
567	OP_MAXSS,
568	OP_MOVDQU,
569	OP_PSHUFHW,
570	OP_CMPSS,
571	OP_MOVQ2DQ,
572	OP_CVTDQ2PD,
573	OP_PERMQ,
574	OP_PERMPD,
575	OP_PBLENDD,
576	OP_PERM2F128,
577	OP_ROUNDPS,
578	OP_ROUNDPD,
579	OP_ROUNDSS,
580	OP_ROUNDSD,
581	OP_BLENDPS,
582	OP_BLENDPD,
583	OP_PBLENDW,
584	OP_PALIGNR,
585	OP_PEXTRB,
586	OP_PEXTRD,
587	OP_PEXTRQ,
588	OP_EXTRACTPS,
589	OP_INSERTF128,
590	OP_EXTRACTF128,
591	OP_CVTPS2PH,
592	OP_PINSRB,
593	OP_PINSRD,
594	OP_PINSRQ,
595	OP_INSERTPS,
596	OP_INSERTI128,
597	OP_EXTRACTI128,
598	OP_DPPS,
599	OP_DPPD,
600	OP_MPSADBW,
601	OP_PCLMULQDQ,
602	OP_PERM2I128,
603	OP_PCMPESTRM,
604	OP_PCMPESTRI,
605	OP_PCMPISTRM,
606	OP_PCMPISTRI,
607	OP_AESKEYGEN,
608	OP_RORX,
609	OP_RDRAND,
610	OP_RDSEED,
611	OP_MOVBE,
612	OP_VEX3B,
613	OP_VEX2B,
614	/** @} */
615
616	/** @name Floating point ops
617	* @{ */
618	OP_FADD,
619	OP_FMUL,
620	OP_FCOM,
621	OP_FCOMP,
622	OP_FSUB,
623	OP_FSUBR,
624	OP_FDIV,
625	OP_FDIVR,
626	OP_FLD,
627	OP_FST,
628	OP_FSTP,
629	OP_FLDENV,
630	OP_FSTENV,
631	OP_FSTCW,
632	OP_FXCH,
633	OP_FNOP,
634	OP_FCHS,
635	OP_FABS,
636	OP_FLD1,
637	OP_FLDL2T,
638	OP_FLDL2E,
639	OP_FLDPI,
640	OP_FLDLG2,
641	OP_FLDLN2,
642	OP_FLDZ,
643	OP_F2XM1,
644	OP_FYL2X,
645	OP_FPTAN,
646	OP_FPATAN,
647	OP_FXTRACT,
648	OP_FREM1,
649	OP_FDECSTP,
650	OP_FINCSTP,
651	OP_FPREM,
652	OP_FYL2XP1,
653	OP_FSQRT,
654	OP_FSINCOS,
655	OP_FRNDINT,
656	OP_FSCALE,
657	OP_FSIN,
658	OP_FCOS,
659	OP_FIADD,
660	OP_FIMUL,
661	OP_FISUB,
662	OP_FISUBR,
663	OP_FIDIV,
664	OP_FIDIVR,
665	OP_FCMOVB,
666	OP_FCMOVE,
667	OP_FCMOVBE,
668	OP_FCMOVU,
669	OP_FUCOMPP,
670	OP_FILD,
671	OP_FIST,
672	OP_FISTP,
673	OP_FCMOVNB,
674	OP_FCMOVNE,
675	OP_FCMOVNBE,
676	OP_FCMOVNU,
677	OP_FCLEX,
678	OP_FINIT,
679	OP_FUCOMI,
680	OP_FCOMI,
681	OP_FRSTOR,
682	OP_FSAVE,
683	OP_FNSTSW,
684	OP_FFREE,
685	OP_FUCOM,
686	OP_FUCOMP,
687	OP_FICOM,
688	OP_FICOMP,
689	OP_FADDP,
690	OP_FMULP,
691	OP_FCOMPP,
692	OP_FSUBRP,
693	OP_FSUBP,
694	OP_FDIVRP,
695	OP_FDIVP,
696	OP_FBLD,
697	OP_FBSTP,
698	OP_FCOMIP,
699	OP_FUCOMIP,
700	/** @} */
701
702	/** @name 3DNow!
703	* @{ */
704	OP_PI2FW,
705	OP_PI2FD,
706	OP_PF2IW,
707	OP_PF2ID,
708	OP_PFPNACC,
709	OP_PFCMPGE,
710	OP_PFMIN,
711	OP_PFRCP,
712	OP_PFRSQRT,
713	OP_PFSUB,
714	OP_PFADD,
715	OP_PFCMPGT,
716	OP_PFMAX,
717	OP_PFRCPIT1,
718	OP_PFRSQRTIT1,
719	OP_PFSUBR,
720	OP_PFACC,
721	OP_PFCMPEQ,
722	OP_PFMUL,
723	OP_PFRCPIT2,
724	OP_PFMULHRW,
725	OP_PFSWAPD,
726	OP_PAVGUSB,
727	OP_PFNACC,
728	/** @} */
729	OP_ROL,
730	OP_ROR,
731	OP_RCL,
732	OP_RCR,
733	OP_SHL,
734	OP_SHR,
735	OP_SAR,
736	OP_NOT,
737	OP_NEG,
738	OP_MUL,
739	OP_DIV,
740	OP_IDIV,
741	OP_SLDT,
742	OP_STR,
743	OP_LLDT,
744	OP_LTR,
745	OP_VERR,
746	OP_VERW,
747	OP_SGDT,
748	OP_LGDT,
749	OP_SIDT,
750	OP_LIDT,
751	OP_SMSW,
752	OP_LMSW,
753	OP_INVLPG,
754	OP_CMPXCHG8B,
755	OP_PSLLQ,
756	OP_PSRLDQ,
757	OP_PSLLDQ,
758	OP_FXSAVE,
759	OP_FXRSTOR,
760	OP_LDMXCSR,
761	OP_STMXCSR,
762	OP_XSAVE,
763	OP_XSAVEOPT,
764	OP_XRSTOR,
765	OP_XGETBV,
766	OP_XSETBV,
767	OP_RDFSBASE,
768	OP_RDGSBASE,
769	OP_WRFSBASE,
770	OP_WRGSBASE,
771	OP_LFENCE,
772	OP_MFENCE,
773	OP_SFENCE,
774	OP_PREFETCH,
775	OP_MONITOR,
776	OP_MWAIT,
777	OP_CLFLUSH,
778	OP_CLFLUSHOPT,
779	OP_MOV_DR,
780	OP_MOV_TR,
781	OP_SWAPGS,
782	OP_UD1,
783	OP_UD2,
784	/** @name VT-x instructions
785	* @{ */
786	OP_VMREAD,
787	OP_VMWRITE,
788	OP_VMCALL,
789	OP_VMXON,
790	OP_VMXOFF,
791	OP_VMCLEAR,
792	OP_VMLAUNCH,
793	OP_VMRESUME,
794	OP_VMPTRLD,
795	OP_VMPTRST,
796	OP_INVEPT,
797	OP_INVVPID,
798	OP_INVPCID,
799	OP_VMFUNC,
800	/** @} */
801	/** @name AMD-V instructions
802	* @{ */
803	OP_VMMCALL,
804	OP_VMRUN,
805	OP_VMLOAD,
806	OP_VMSAVE,
807	OP_CLGI,
808	OP_STGI,
809	OP_INVLPGA,
810	OP_SKINIT,
811	/** @} */
812	/** @name 64 bits instruction
813	* @{ */
814	OP_MOVSXD,
815	/** @} */
816	/** @name AVX instructions
817	* @{ */
818	/* Manual */
819	OP_VSTMXCSR,
820	OP_VLDMXCSR,
821	OP_VPACKUSDW,
822
823	/* Generated from tables: */
824	OP_VADDPD,
825	OP_VADDPS,
826	OP_VADDSD,
827	OP_VADDSS,
828	OP_VADDSUBPD,
829	OP_VADDSUBPS,
830	OP_VAESDEC,
831	OP_VAESDECLAST,
832	OP_VAESENC,
833	OP_VAESENCLAST,
834	OP_VAESIMC,
835	OP_VAESKEYGEN,
836	OP_VANDNPD,
837	OP_VANDNPS,
838	OP_VANDPD,
839	OP_VANDPS,
840	OP_VBLENDPD,
841	OP_VBLENDPS,
842	OP_VBLENDVPD,
843	OP_VBLENDVPS,
844	OP_VBROADCASTF128,
845	OP_VBROADCASTSD,
846	OP_VBROADCASTSS,
847	OP_VCMPSD,
848	OP_VCMPSS,
849	OP_VCOMISD,
850	OP_VCOMISS,
851	OP_VCVTDQ2PD,
852	OP_VCVTDQ2PS,
853	OP_VCVTPD2DQ,
854	OP_VCVTPD2PS,
855	OP_VCVTPH2PS,
856	OP_VCVTPS2DQ,
857	OP_VCVTPS2PD,
858	OP_VCVTPS2PH,
859	OP_VCVTSD2SS,
860	OP_VCVTSI2SS,
861	OP_VCVTSS2SD,
862	OP_VCVTSS2SI,
863	OP_VCVTTPD2DQ,
864	OP_VCVTTPS2DQ,
865	OP_VCVTTSS2SI,
866	OP_VDIVPD,
867	OP_VDIVPS,
868	OP_VDIVSD,
869	OP_VDIVSS,
870	OP_VDPPD,
871	OP_VDPPS,
872	OP_VEXTRACTF128,
873	OP_VEXTRACTI128,
874	OP_VEXTRACTPS,
875	OP_VFMADD132PS,
876	OP_VFMADD132SS,
877	OP_VFMADD213PS,
878	OP_VFMADD213SS,
879	OP_VFMADD231PS,
880	OP_VFMADD231SS,
881	OP_VFMADDSUB132PS,
882	OP_VFMADDSUB213PS,
883	OP_VFMADDSUB231PS,
884	OP_VFMSUB132PS,
885	OP_VFMSUB132SS,
886	OP_VFMSUB213PS,
887	OP_VFMSUB213SS,
888	OP_VFMSUB231PS,
889	OP_VFMSUB231SS,
890	OP_VFMSUBADD132PS,
891	OP_VFMSUBADD213PS,
892	OP_VFMSUBADD231PS,
893	OP_VFNMADD132PS,
894	OP_VFNMADD132SS,
895	OP_VFNMADD213PS,
896	OP_VFNMADD213SS,
897	OP_VFNMADD231PS,
898	OP_VFNMADD231SS,
899	OP_VFNMSUB132PS,
900	OP_VFNMSUB132SS,
901	OP_VFNMSUB213PS,
902	OP_VFNMSUB213SS,
903	OP_VFNMSUB231PS,
904	OP_VFNMSUB231SS,
905	OP_VGATHER,
906	OP_VHADDPD,
907	OP_VHADDPS,
908	OP_VHSUBPD,
909	OP_VHSUBPS,
910	OP_VINSERTF128,
911	OP_VINSERTI128,
912	OP_VINSERTPS,
913	OP_VLDDQU,
914	OP_VMASKMOVDQU,
915	OP_VMASKMOVPD,
916	OP_VMASKMOVPS,
917	OP_VMAXPD,
918	OP_VMAXPS,
919	OP_VMAXSD,
920	OP_VMAXSS,
921	OP_VMINPD,
922	OP_VMINPS,
923	OP_VMINSD,
924	OP_VMINSS,
925	OP_VMOVAPD,
926	OP_VMOVAPS,
927	OP_VMOVD,
928	OP_VMOVDDUP,
929	OP_VMOVDQA,
930	OP_VMOVDQU,
931	OP_VMOVHPD,
932	OP_VMOVHPS,
933	OP_VMOVLHPS = OP_VMOVHPS, /*< @todo OP_VMOVHPS /
934	OP_VMOVLPD,
935	OP_VMOVLPS,
936	OP_VMOVHLPS = OP_VMOVLPS, /*< @todo OP_VMOVLPS /
937	OP_VMOVMSKPD,
938	OP_VMOVMSKPS,
939	OP_VMOVNTDQ,
940	OP_VMOVNTDQA,
941	OP_VMOVNTPD,
942	OP_VMOVNTPS,
943	OP_VMOVQ,
944	OP_VMOVSD,
945	OP_VMOVSHDUP,
946	OP_VMOVSLDUP,
947	OP_VMOVSS,
948	OP_VMOVUPD,
949	OP_VMOVUPS,
950	OP_VMPSADBW,
951	OP_VMULPD,
952	OP_VMULPS,
953	OP_VMULSD,
954	OP_VMULSS,
955	OP_VORPD,
956	OP_VORPS,
957	OP_VPABSB,
958	OP_VPABSD,
959	OP_VPABSW,
960	OP_VPACKSSDW,
961	OP_VPACKSSWB,
962	OP_VPACKUSWB,
963	OP_VPADDB,
964	OP_VPADDD,
965	OP_VPADDQ,
966	OP_VPADDSB,
967	OP_VPADDSW,
968	OP_VPADDUSB,
969	OP_VPADDUSW,
970	OP_VPADDW,
971	OP_VPALIGNR,
972	OP_VPAND,
973	OP_VPANDN,
974	OP_VPAVGB,
975	OP_VPAVGW,
976	OP_VPBLENDD,
977	OP_VPBLENDVB,
978	OP_VPBLENDW,
979	OP_VPBROADCASTB,
980	OP_VPBROADCASTD,
981	OP_VPBROADCASTI128,
982	OP_VPBROADCASTQ,
983	OP_VPBROADCASTW,
984	OP_VPCLMULQDQ,
985	OP_VPCMPEQB,
986	OP_VPCMPEQD,
987	OP_VPCMPEQQ,
988	OP_VPCMPEQW,
989	OP_VPCMPESTRI,
990	OP_VPCMPESTRM,
991	OP_VPCMPGTB,
992	OP_VPCMPGTD,
993	OP_VPCMPGTQ,
994	OP_VPCMPGTW,
995	OP_VPCMPISTRI,
996	OP_VPCMPISTRM,
997	OP_VPERM2F128,
998	OP_VPERM2I128,
999	OP_VPERMD,
1000	OP_VPERMILPD,
1001	OP_VPERMILPS,
1002	OP_VPERMPD,
1003	OP_VPERMPS,
1004	OP_VPERMQ,
1005	OP_VPEXTRB,
1006	OP_VPEXTRD,
1007	OP_VPEXTRW,
1008	OP_VPEXTRQ,
1009	OP_VPHADDD,
1010	OP_VPHADDSW,
1011	OP_VPHADDW,
1012	OP_VPHMINPOSUW,
1013	OP_VPHSUBD,
1014	OP_VPHSUBSW,
1015	OP_VPHSUBW,
1016	OP_VPINSRB,
1017	OP_VPINSRD,
1018	OP_VPINSRW,
1019	OP_VPINSRQ,
1020	OP_VPMADDUBSW,
1021	OP_VPMADDWD,
1022	OP_VPMASKMOVD,
1023	OP_VPMAXSB,
1024	OP_VPMAXSD,
1025	OP_VPMAXSW,
1026	OP_VPMAXUB,
1027	OP_VPMAXUD,
1028	OP_VPMAXUW,
1029	OP_VPMINSB,
1030	OP_VPMINSD,
1031	OP_VPMINSW,
1032	OP_VPMINUB,
1033	OP_VPMINUD,
1034	OP_VPMINUW,
1035	OP_VPMOVMSKB,
1036	OP_VPMOVSXBW,
1037	OP_VPMOVSXBD,
1038	OP_VPMOVSXBQ,
1039	OP_VPMOVSXWD,
1040	OP_VPMOVSXWQ,
1041	OP_VPMOVSXDQ,
1042	OP_VPMOVZXBW,
1043	OP_VPMOVZXBD,
1044	OP_VPMOVZXBQ,
1045	OP_VPMOVZXWD,
1046	OP_VPMOVZXWQ,
1047	OP_VPMOVZXDQ,
1048	OP_VPMULDQ,
1049	OP_VPMULHRSW,
1050	OP_VPMULHUW,
1051	OP_VPMULHW,
1052	OP_VPMULLD,
1053	OP_VPMULLW,
1054	OP_VPMULUDQ,
1055	OP_VPOR,
1056	OP_VPSADBW,
1057	OP_VPSHUFB,
1058	OP_VPSHUFD,
1059	OP_VPSHUFHW,
1060	OP_VPSHUFLW,
1061	OP_VPSIGNB,
1062	OP_VPSIGND,
1063	OP_VPSIGNW,
1064	OP_VPSLLD,
1065	OP_VPSLLQ,
1066	OP_VPSLLVD,
1067	OP_VPSLLW,
1068	OP_VPSRAD,
1069	OP_VPSRAVD,
1070	OP_VPSRAW,
1071	OP_VPSRLD,
1072	OP_VPSRLQ,
1073	OP_VPSRLVD,
1074	OP_VPSRLW,
1075	OP_VPSUBB,
1076	OP_VPSUBD,
1077	OP_VPSUBQ,
1078	OP_VPSUBSB,
1079	OP_VPSUBSW,
1080	OP_VPSUBUSB,
1081	OP_VPSUBUSW,
1082	OP_VPSUBW,
1083	OP_VPTEST,
1084	OP_VPUNPCKHBW,
1085	OP_VPUNPCKHDQ,
1086	OP_VPUNPCKHQDQ,
1087	OP_VPUNPCKHWD,
1088	OP_VPUNPCKLBW,
1089	OP_VPUNPCKLDQ,
1090	OP_VPUNPCKLQDQ,
1091	OP_VPUNPCKLWD,
1092	OP_VPXOR,
1093	OP_VRCPPS,
1094	OP_VRCPSS,
1095	OP_VROUNDPD,
1096	OP_VROUNDPS,
1097	OP_VROUNDSD,
1098	OP_VROUNDSS,
1099	OP_VRSQRTPS,
1100	OP_VRSQRTSS,
1101	OP_VSHUFPD,
1102	OP_VSHUFPS,
1103	OP_VSQRTPD,
1104	OP_VSQRTPS,
1105	OP_VSQRTSD,
1106	OP_VSQRTSS,
1107	OP_VSUBPD,
1108	OP_VSUBPS,
1109	OP_VSUBSD,
1110	OP_VSUBSS,
1111	OP_VTESTPD,
1112	OP_VTESTPS,
1113	OP_VUCOMISD,
1114	OP_VUCOMISS,
1115	OP_VUNPCKHPD,
1116	OP_VUNPCKHPS,
1117	OP_VUNPCKLPD,
1118	OP_VUNPCKLPS,
1119	OP_VVPACKUSDW,
1120	OP_VXORPD,
1121	OP_VXORPS,
1122	OP_VZEROALL,
1123
1124	/** @} */
1125	OP_END_OF_OPCODES
1126	};
1127	AssertCompile(OP_LOCK == 7);
1128	#if 0
1129	AssertCompile(OP_END_OF_OPCODES < 1024 /* see 15 byte DISOPCODE variant */);
1130	#endif
1131	/** @} */
1132
1133
1134	/** @defgroup grp_dis_opparam Opcode parameters (DISOPCODE::fParam1,
1135	* DISOPCODE::fParam2, DISOPCODE::fParam3)
1136	* @ingroup grp_dis
1137	* @{
1138	*/
1139
1140	/**
1141	* @remarks Register order is important for translations!!
1142	*/
1143	enum OP_PARM
1144	{
1145	OP_PARM_NONE,
1146
1147	OP_PARM_REG_EAX,
1148	OP_PARM_REG_GEN32_START = OP_PARM_REG_EAX,
1149	OP_PARM_REG_ECX,
1150	OP_PARM_REG_EDX,
1151	OP_PARM_REG_EBX,
1152	OP_PARM_REG_ESP,
1153	OP_PARM_REG_EBP,
1154	OP_PARM_REG_ESI,
1155	OP_PARM_REG_EDI,
1156	OP_PARM_REG_GEN32_END = OP_PARM_REG_EDI,
1157
1158	OP_PARM_REG_ES,
1159	OP_PARM_REG_SEG_START = OP_PARM_REG_ES,
1160	OP_PARM_REG_CS,
1161	OP_PARM_REG_SS,
1162	OP_PARM_REG_DS,
1163	OP_PARM_REG_FS,
1164	OP_PARM_REG_GS,
1165	OP_PARM_REG_SEG_END = OP_PARM_REG_GS,
1166
1167	OP_PARM_REG_AX,
1168	OP_PARM_REG_GEN16_START = OP_PARM_REG_AX,
1169	OP_PARM_REG_CX,
1170	OP_PARM_REG_DX,
1171	OP_PARM_REG_BX,
1172	OP_PARM_REG_SP,
1173	OP_PARM_REG_BP,
1174	OP_PARM_REG_SI,
1175	OP_PARM_REG_DI,
1176	OP_PARM_REG_GEN16_END = OP_PARM_REG_DI,
1177
1178	OP_PARM_REG_AL,
1179	OP_PARM_REG_GEN8_START = OP_PARM_REG_AL,
1180	OP_PARM_REG_CL,
1181	OP_PARM_REG_DL,
1182	OP_PARM_REG_BL,
1183	OP_PARM_REG_AH,
1184	OP_PARM_REG_CH,
1185	OP_PARM_REG_DH,
1186	OP_PARM_REG_BH,
1187	OP_PARM_REG_GEN8_END = OP_PARM_REG_BH,
1188
1189	OP_PARM_REGFP_0,
1190	OP_PARM_REG_FP_START = OP_PARM_REGFP_0,
1191	OP_PARM_REGFP_1,
1192	OP_PARM_REGFP_2,
1193	OP_PARM_REGFP_3,
1194	OP_PARM_REGFP_4,
1195	OP_PARM_REGFP_5,
1196	OP_PARM_REGFP_6,
1197	OP_PARM_REGFP_7,
1198	OP_PARM_REG_FP_END = OP_PARM_REGFP_7,
1199
1200	OP_PARM_NTA,
1201	OP_PARM_T0,
1202	OP_PARM_T1,
1203	OP_PARM_T2,
1204	OP_PARM_1,
1205
1206	OP_PARM_REX,
1207	OP_PARM_REX_START = OP_PARM_REX,
1208	OP_PARM_REX_B,
1209	OP_PARM_REX_X,
1210	OP_PARM_REX_XB,
1211	OP_PARM_REX_R,
1212	OP_PARM_REX_RB,
1213	OP_PARM_REX_RX,
1214	OP_PARM_REX_RXB,
1215	OP_PARM_REX_W,
1216	OP_PARM_REX_WB,
1217	OP_PARM_REX_WX,
1218	OP_PARM_REX_WXB,
1219	OP_PARM_REX_WR,
1220	OP_PARM_REX_WRB,
1221	OP_PARM_REX_WRX,
1222	OP_PARM_REX_WRXB,
1223
1224	OP_PARM_REG_RAX,
1225	OP_PARM_REG_GEN64_START = OP_PARM_REG_RAX,
1226	OP_PARM_REG_RCX,
1227	OP_PARM_REG_RDX,
1228	OP_PARM_REG_RBX,
1229	OP_PARM_REG_RSP,
1230	OP_PARM_REG_RBP,
1231	OP_PARM_REG_RSI,
1232	OP_PARM_REG_RDI,
1233	OP_PARM_REG_R8,
1234	OP_PARM_REG_R9,
1235	OP_PARM_REG_R10,
1236	OP_PARM_REG_R11,
1237	OP_PARM_REG_R12,
1238	OP_PARM_REG_R13,
1239	OP_PARM_REG_R14,
1240	OP_PARM_REG_R15,
1241	OP_PARM_REG_GEN64_END = OP_PARM_REG_R15
1242	};
1243
1244
1245	/* 8-bit GRP aliases (for IEM). */
1246	#define OP_PARM_AL OP_PARM_REG_AL
1247
1248	/* GPR aliases for op-size specified register sizes (for IEM). */
1249	#define OP_PARM_rAX OP_PARM_REG_EAX
1250	#define OP_PARM_rCX OP_PARM_REG_ECX
1251	#define OP_PARM_rDX OP_PARM_REG_EDX
1252	#define OP_PARM_rBX OP_PARM_REG_EBX
1253	#define OP_PARM_rSP OP_PARM_REG_ESP
1254	#define OP_PARM_rBP OP_PARM_REG_EBP
1255	#define OP_PARM_rSI OP_PARM_REG_ESI
1256	#define OP_PARM_rDI OP_PARM_REG_EDI
1257
1258	/* SREG aliases (for IEM). */
1259	#define OP_PARM_ES OP_PARM_REG_ES
1260	#define OP_PARM_CS OP_PARM_REG_CS
1261	#define OP_PARM_SS OP_PARM_REG_SS
1262	#define OP_PARM_DS OP_PARM_REG_DS
1263	#define OP_PARM_FS OP_PARM_REG_FS
1264	#define OP_PARM_GS OP_PARM_REG_GS
1265
1266	/*
1267	* Note! We don't document anything here if we can help it, because it we love
1268	* wasting other peoples time figuring out crypting crap. The new VEX
1269	* stuff of course uphelds this vexing tradition. Aaaaaaaaaaaaaaaaaaarg!
1270	*/
1271
1272	#define OP_PARM_VTYPE(a) ((unsigned)a & 0xFE0)
1273	#define OP_PARM_VSUBTYPE(a) ((unsigned)a & 0x01F)
1274
1275	#define OP_PARM_A 0x100
1276	#define OP_PARM_VARIABLE OP_PARM_A
1277	#define OP_PARM_E 0x120
1278	#define OP_PARM_F 0x140
1279	#define OP_PARM_G 0x160
1280	#define OP_PARM_I 0x180
1281	#define OP_PARM_J 0x1A0
1282	#define OP_PARM_M 0x1C0
1283	#define OP_PARM_O 0x1E0
1284	#define OP_PARM_R 0x200
1285	#define OP_PARM_X 0x220
1286	#define OP_PARM_Y 0x240
1287
1288	/* Grouped rare parameters for optimization purposes */
1289	#define IS_OP_PARM_RARE(a) ((a & 0xF00) >= 0x300)
1290	#define OP_PARM_C 0x300 /* control register */
1291	#define OP_PARM_D 0x320 /* debug register */
1292	#define OP_PARM_S 0x340 /* segment register */
1293	#define OP_PARM_T 0x360 /* test register */
1294	#define OP_PARM_Q 0x380
1295	#define OP_PARM_P 0x3A0 /* mmx register */
1296	#define OP_PARM_W 0x3C0 /* xmm register */
1297	#define OP_PARM_V 0x3E0
1298	#define OP_PARM_U 0x400 /* The R/M field of the ModR/M byte selects XMM/YMM register. */
1299	#define OP_PARM_B 0x420 /* VEX.vvvv field select general purpose register. */
1300	#define OP_PARM_H 0x440
1301	#define OP_PARM_L 0x460
1302
1303	#define OP_PARM_NONE 0
1304	#define OP_PARM_a 0x1 /*< Operand to bound instruction. /
1305	#define OP_PARM_b 0x2 /*< Byte (always). /
1306	#define OP_PARM_d 0x3 /*< Double word (always). /
1307	#define OP_PARM_dq 0x4 /*< Double quad word (always). /
1308	#define OP_PARM_p 0x5 /*< Far pointer (subject to opsize). /
1309	#define OP_PARM_pd 0x6 /*< 128-bit or 256-bit double precision floating point data. /
1310	#define OP_PARM_pi 0x7 /*< Quad word MMX register. /
1311	#define OP_PARM_ps 0x8 /*< 128-bit or 256-bit single precision floating point data. /
1312	#define OP_PARM_q 0xA /*< Quad word (always). /
1313	#define OP_PARM_s 0xB /*< Descriptor table size (SIDT/LIDT/SGDT/LGDT). /
1314	#define OP_PARM_sd 0xC /*< Scalar element of 128-bit double precision floating point data. /
1315	#define OP_PARM_ss 0xD /*< Scalar element of 128-bit single precision floating point data. /
1316	#define OP_PARM_v 0xE /*< Word, double word, or quad word depending on opsize. /
1317	#define OP_PARM_w 0xF /*< Word (always). /
1318	#define OP_PARM_x 0x10 /*< Double quad word (dq) or quad quad word (qq) depending on opsize. /
1319	#define OP_PARM_y 0x11 /*< Double word or quad word depending on opsize. /
1320	#define OP_PARM_z 0x12 /*< Word (16-bit opsize) or double word (32-bit/64-bit opsize). /
1321	#define OP_PARM_qq 0x13 /*< Quad quad word. /
1322
1323
1324	#define OP_PARM_Ap (OP_PARM_A+OP_PARM_p)
1325	#define OP_PARM_By (OP_PARM_B+OP_PARM_y)
1326	#define OP_PARM_Cd (OP_PARM_C+OP_PARM_d)
1327	#define OP_PARM_Dd (OP_PARM_D+OP_PARM_d)
1328	#define OP_PARM_Eb (OP_PARM_E+OP_PARM_b)
1329	#define OP_PARM_Ed (OP_PARM_E+OP_PARM_d)
1330	#define OP_PARM_Ep (OP_PARM_E+OP_PARM_p)
1331	#define OP_PARM_Ev (OP_PARM_E+OP_PARM_v)
1332	#define OP_PARM_Ew (OP_PARM_E+OP_PARM_w)
1333	#define OP_PARM_Ey (OP_PARM_E+OP_PARM_y)
1334	#define OP_PARM_Fv (OP_PARM_F+OP_PARM_v)
1335	#define OP_PARM_Gb (OP_PARM_G+OP_PARM_b)
1336	#define OP_PARM_Gd (OP_PARM_G+OP_PARM_d)
1337	#define OP_PARM_Gv (OP_PARM_G+OP_PARM_v)
1338	#define OP_PARM_Gw (OP_PARM_G+OP_PARM_w)
1339	#define OP_PARM_Gy (OP_PARM_G+OP_PARM_y)
1340	#define OP_PARM_Hq (OP_PARM_H+OP_PARM_q)
1341	#define OP_PARM_Hps (OP_PARM_H+OP_PARM_ps)
1342	#define OP_PARM_Hpd (OP_PARM_H+OP_PARM_pd)
1343	#define OP_PARM_Hdq (OP_PARM_H+OP_PARM_dq)
1344	#define OP_PARM_Hqq (OP_PARM_H+OP_PARM_qq)
1345	#define OP_PARM_Hsd (OP_PARM_H+OP_PARM_sd)
1346	#define OP_PARM_Hss (OP_PARM_H+OP_PARM_ss)
1347	#define OP_PARM_Hx (OP_PARM_H+OP_PARM_x)
1348	#define OP_PARM_Ib (OP_PARM_I+OP_PARM_b)
1349	#define OP_PARM_Id (OP_PARM_I+OP_PARM_d)
1350	#define OP_PARM_Iq (OP_PARM_I+OP_PARM_q)
1351	#define OP_PARM_Iw (OP_PARM_I+OP_PARM_w)
1352	#define OP_PARM_Iv (OP_PARM_I+OP_PARM_v)
1353	#define OP_PARM_Iz (OP_PARM_I+OP_PARM_z)
1354	#define OP_PARM_Jb (OP_PARM_J+OP_PARM_b)
1355	#define OP_PARM_Jv (OP_PARM_J+OP_PARM_v)
1356	#define OP_PARM_Ma (OP_PARM_M+OP_PARM_a)
1357	#define OP_PARM_Mb (OP_PARM_M+OP_PARM_b)
1358	#define OP_PARM_Mw (OP_PARM_M+OP_PARM_w)
1359	#define OP_PARM_Md (OP_PARM_M+OP_PARM_d)
1360	#define OP_PARM_Mp (OP_PARM_M+OP_PARM_p)
1361	#define OP_PARM_Mq (OP_PARM_M+OP_PARM_q)
1362	#define OP_PARM_Mdq (OP_PARM_M+OP_PARM_dq)
1363	#define OP_PARM_Ms (OP_PARM_M+OP_PARM_s)
1364	#define OP_PARM_Mx (OP_PARM_M+OP_PARM_x)
1365	#define OP_PARM_My (OP_PARM_M+OP_PARM_y)
1366	#define OP_PARM_Mps (OP_PARM_M+OP_PARM_ps)
1367	#define OP_PARM_Mpd (OP_PARM_M+OP_PARM_pd)
1368	#define OP_PARM_Ob (OP_PARM_O+OP_PARM_b)
1369	#define OP_PARM_Ov (OP_PARM_O+OP_PARM_v)
1370	#define OP_PARM_Pq (OP_PARM_P+OP_PARM_q)
1371	#define OP_PARM_Pd (OP_PARM_P+OP_PARM_d)
1372	#define OP_PARM_Qd (OP_PARM_Q+OP_PARM_d)
1373	#define OP_PARM_Qq (OP_PARM_Q+OP_PARM_q)
1374	#define OP_PARM_Rd (OP_PARM_R+OP_PARM_d)
1375	#define OP_PARM_Rw (OP_PARM_R+OP_PARM_w)
1376	#define OP_PARM_Ry (OP_PARM_R+OP_PARM_y)
1377	#define OP_PARM_Sw (OP_PARM_S+OP_PARM_w)
1378	#define OP_PARM_Td (OP_PARM_T+OP_PARM_d)
1379	#define OP_PARM_Ux (OP_PARM_U+OP_PARM_x)
1380	#define OP_PARM_Vq (OP_PARM_V+OP_PARM_q)
1381	#define OP_PARM_Vx (OP_PARM_V+OP_PARM_x)
1382	#define OP_PARM_Vy (OP_PARM_V+OP_PARM_y)
1383	#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1384	/#define OP_PARM_Ws (OP_PARM_W+OP_PARM_s) - wtf? Same as lgdt (OP_PARM_Ms)?/
1385	#define OP_PARM_Wx (OP_PARM_W+OP_PARM_x)
1386	#define OP_PARM_Xb (OP_PARM_X+OP_PARM_b)
1387	#define OP_PARM_Xv (OP_PARM_X+OP_PARM_v)
1388	#define OP_PARM_Yb (OP_PARM_Y+OP_PARM_b)
1389	#define OP_PARM_Yv (OP_PARM_Y+OP_PARM_v)
1390
1391	#define OP_PARM_Vps (OP_PARM_V+OP_PARM_ps)
1392	#define OP_PARM_Vss (OP_PARM_V+OP_PARM_ss)
1393	#define OP_PARM_Vpd (OP_PARM_V+OP_PARM_pd)
1394	#define OP_PARM_Vdq (OP_PARM_V+OP_PARM_dq)
1395	#define OP_PARM_Wps (OP_PARM_W+OP_PARM_ps)
1396	#define OP_PARM_Wpd (OP_PARM_W+OP_PARM_pd)
1397	#define OP_PARM_Wss (OP_PARM_W+OP_PARM_ss)
1398	#define OP_PARM_Ww (OP_PARM_W+OP_PARM_w)
1399	#define OP_PARM_Wd (OP_PARM_W+OP_PARM_d)
1400	#define OP_PARM_Wq (OP_PARM_W+OP_PARM_q)
1401	#define OP_PARM_Wdq (OP_PARM_W+OP_PARM_dq)
1402	#define OP_PARM_Wqq (OP_PARM_W+OP_PARM_qq)
1403	#define OP_PARM_Ppi (OP_PARM_P+OP_PARM_pi)
1404	#define OP_PARM_Qpi (OP_PARM_Q+OP_PARM_pi)
1405	#define OP_PARM_Qdq (OP_PARM_Q+OP_PARM_dq)
1406	#define OP_PARM_Vsd (OP_PARM_V+OP_PARM_sd)
1407	#define OP_PARM_Wsd (OP_PARM_W+OP_PARM_sd)
1408	#define OP_PARM_Vqq (OP_PARM_V+OP_PARM_qq)
1409	#define OP_PARM_Pdq (OP_PARM_P+OP_PARM_dq)
1410	#define OP_PARM_Ups (OP_PARM_U+OP_PARM_ps)
1411	#define OP_PARM_Upd (OP_PARM_U+OP_PARM_pd)
1412	#define OP_PARM_Udq (OP_PARM_U+OP_PARM_dq)
1413	#define OP_PARM_Lx (OP_PARM_L+OP_PARM_x)
1414
1415	/* For making IEM / bs3-cpu-generated-1 happy: */
1416	#define OP_PARM_Ed_WO OP_PARM_Ed /*< Annotates write only operand. /
1417	#define OP_PARM_Eq (OP_PARM_E+OP_PARM_q)
1418	#define OP_PARM_Eq_WO OP_PARM_Eq /*< Annotates write only operand. /
1419	#define OP_PARM_Gv_RO OP_PARM_Gv /*< Annotates read only first operand (default is readwrite). /
1420	#define OP_PARM_HssHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:32]. /
1421	#define OP_PARM_HsdHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:64]. /
1422	#define OP_PARM_HqHi OP_PARM_Hx /*< Register referenced by VEX.vvvv, bits [127:64]. /
1423	#define OP_PARM_M_RO OP_PARM_M /*< Annotates read only memory of variable operand size (xrstor). /
1424	#define OP_PARM_M_RW OP_PARM_M /*< Annotates read-write memory of variable operand size (xsave). /
1425	#define OP_PARM_Mb_RO OP_PARM_Mb /*< Annotates read only memory byte operand. /
1426	#define OP_PARM_Md_RO OP_PARM_Md /*< Annotates read only memory operand. /
1427	#define OP_PARM_Md_WO OP_PARM_Md /*< Annotates write only memory operand. /
1428	#define OP_PARM_Mdq_WO OP_PARM_Mdq /*< Annotates write only memory operand. /
1429	#define OP_PARM_Mq_WO OP_PARM_Mq /*< Annotates write only memory quad word operand. /
1430	#define OP_PARM_Mps_WO OP_PARM_Mps /*< Annotates write only memory operand. /
1431	#define OP_PARM_Mpd_WO OP_PARM_Mpd /*< Annotates write only memory operand. /
1432	#define OP_PARM_Mx_WO OP_PARM_Mx /*< Annotates write only memory operand. /
1433	#define OP_PARM_PdZx_WO OP_PARM_Pd /*< Annotates write only operand and zero extends to 64-bit. /
1434	#define OP_PARM_Pq_WO OP_PARM_Pq /*< Annotates write only operand. /
1435	#define OP_PARM_Qq_WO OP_PARM_Qq /*< Annotates write only operand. /
1436	#define OP_PARM_Nq OP_PARM_Qq /*< Missing 'N' class (MMX reg selected by modrm.mem) in disasm. /
1437	#define OP_PARM_Uq (OP_PARM_U+OP_PARM_q)
1438	#define OP_PARM_UqHi (OP_PARM_U+OP_PARM_dq)
1439	#define OP_PARM_Uss (OP_PARM_U+OP_PARM_ss)
1440	#define OP_PARM_Uss_WO OP_PARM_Uss /*< Annotates write only operand. /
1441	#define OP_PARM_Usd (OP_PARM_U+OP_PARM_sd)
1442	#define OP_PARM_Usd_WO OP_PARM_Usd /*< Annotates write only operand. /
1443	#define OP_PARM_Vd (OP_PARM_V+OP_PARM_d)
1444	#define OP_PARM_Vd_WO OP_PARM_Vd /*< Annotates write only operand. /
1445	#define OP_PARM_VdZx_WO OP_PARM_Vd /*< Annotates that the registers get their upper bits cleared /
1446	#define OP_PARM_Vdq_WO OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are accessed. /
1447	#define OP_PARM_Vpd_WO OP_PARM_Vpd /*< Annotates write only operand. /
1448	#define OP_PARM_Vps_WO OP_PARM_Vps /*< Annotates write only operand. /
1449	#define OP_PARM_Vq_WO OP_PARM_Vq /*< Annotates write only operand. /
1450	#define OP_PARM_VqHi OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are accessed. /
1451	#define OP_PARM_VqHi_WO OP_PARM_Vdq /*< Annotates that only YMM/XMM[127:64] are written. /
1452	#define OP_PARM_VqZx_WO OP_PARM_Vq /*< Annotates that the registers get their upper bits cleared /
1453	#define OP_PARM_VsdZx_WO OP_PARM_Vsd /*< Annotates that the registers get their upper bits cleared. /
1454	#define OP_PARM_VssZx_WO OP_PARM_Vss /*< Annotates that the registers get their upper bits cleared. /
1455	#define OP_PARM_Vss_WO OP_PARM_Vss /*< Annotates write only operand. /
1456	#define OP_PARM_Vsd_WO OP_PARM_Vsd /*< Annotates write only operand. /
1457	#define OP_PARM_Vx_WO OP_PARM_Vx /*< Annotates write only operand. /
1458	#define OP_PARM_Wpd_WO OP_PARM_Wpd /*< Annotates write only operand. /
1459	#define OP_PARM_Wps_WO OP_PARM_Wps /*< Annotates write only operand. /
1460	#define OP_PARM_Wq_WO OP_PARM_Wq /*< Annotates write only operand. /
1461	#define OP_PARM_WqZxReg_WO OP_PARM_Wq /*< Annotates that register targets get their upper bits cleared. /
1462	#define OP_PARM_Wss_WO OP_PARM_Wss /*< Annotates write only operand. /
1463	#define OP_PARM_Wsd_WO OP_PARM_Wsd /*< Annotates write only operand. /
1464	#define OP_PARM_Wx_WO OP_PARM_Wx /*< Annotates write only operand. /
1465
1466	/** @} */
1467
1468	#endif /* !VBOX_INCLUDED_disopcode_h */
1469

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source: vbox/trunk/include/VBox/disopcode.h@ 98264

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