VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 91688

Last change on this file since 91688 was 85121, checked in by vboxsync, 4 years ago

iprt/cdefs.h: Refactored the typedef use of DECLCALLBACK as well as DECLCALLBACKMEMBER to wrap the whole expression, similar to the DECLR?CALLBACKMEMBER macros. This allows adding a throw() at the end when compiling with the VC++ compiler to indicate that the callbacks won't throw anything, so we can stop supressing the C5039 warning about passing functions that can potential throw C++ exceptions to extern C code that can't necessarily cope with such (unwind,++). Introduced a few _EX variations that allows specifying different/no calling convention too, as that's handy when dynamically resolving host APIs. Fixed numerous places missing DECLCALLBACK and such. Left two angry @todos regarding use of CreateThread. bugref:9794
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1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef VBOX_INCLUDED_dis_h
27#define VBOX_INCLUDED_dis_h
28#ifndef RT_WITHOUT_PRAGMA_ONCE
29# pragma once
30#endif
31
32#include <VBox/types.h>
33#include <VBox/disopcode.h>
34#include <iprt/assert.h>
35
36
37RT_C_DECLS_BEGIN
38
39/** @defgroup grp_dis VBox Disassembler
40 * @{ */
41
42/** @name Prefix byte flags (DISSTATE::fPrefix).
43 * @{
44 */
45#define DISPREFIX_NONE UINT8_C(0x00)
46/** non-default address size. */
47#define DISPREFIX_ADDRSIZE UINT8_C(0x01)
48/** non-default operand size. */
49#define DISPREFIX_OPSIZE UINT8_C(0x02)
50/** lock prefix. */
51#define DISPREFIX_LOCK UINT8_C(0x04)
52/** segment prefix. */
53#define DISPREFIX_SEG UINT8_C(0x08)
54/** rep(e) prefix (not a prefix, but we'll treat is as one). */
55#define DISPREFIX_REP UINT8_C(0x10)
56/** rep(e) prefix (not a prefix, but we'll treat is as one). */
57#define DISPREFIX_REPNE UINT8_C(0x20)
58/** REX prefix (64 bits) */
59#define DISPREFIX_REX UINT8_C(0x40)
60/** @} */
61
62/** @name VEX.Lvvvv prefix destination register flag.
63 * @{
64 */
65#define VEX_LEN256 UINT8_C(0x01)
66#define VEXREG_IS256B(x) ((x) & VEX_LEN256)
67/* Convert second byte of VEX prefix to internal format */
68#define VEX_2B2INT(x) ((((x) >> 2) & 0x1f))
69#define VEX_HAS_REX_R(x) (!((x) & 0x80))
70
71#define DISPREFIX_VEX_FLAG_W UINT8_C(0x01)
72 /** @} */
73
74/** @name 64 bits prefix byte flags (DISSTATE::fRexPrefix).
75 * Requires VBox/disopcode.h.
76 * @{
77 */
78#define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
79/*#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX) - 0, which is no flag */
80#define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
81#define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
82#define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
83#define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
84#define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
85#define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
86#define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
87#define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
88#define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
89#define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
90#define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
91#define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
92#define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
93#define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
94#define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
95/** @} */
96AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_B));
97AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_X));
98AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_W));
99AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_R));
100
101/** @name Operand type (DISOPCODE::fOpType).
102 * @{
103 */
104#define DISOPTYPE_INVALID RT_BIT_32(0)
105#define DISOPTYPE_HARMLESS RT_BIT_32(1)
106#define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
107#define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
108#define DISOPTYPE_DANGEROUS RT_BIT_32(4)
109#define DISOPTYPE_PORTIO RT_BIT_32(5)
110#define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
111#define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
112#define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
113#define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
114#define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
115#define DISOPTYPE_INTERRUPT RT_BIT_32(11)
116#define DISOPTYPE_ILLEGAL RT_BIT_32(12)
117#define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /**< Some additional dangerous ones when recompiling raw r0. */
118#define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /**< Some additional dangerous ones when recompiling 16-bit raw r0. */
119#define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_RRM_DANGEROUS_16)
120#define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
121#define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
122#define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
123#define DISOPTYPE_INVALID_64 RT_BIT_32(19) /**< Invalid in 64 bits mode */
124#define DISOPTYPE_ONLY_64 RT_BIT_32(20) /**< Only valid in 64 bits mode */
125#define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /**< Default 64 bits operand size */
126#define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
127#define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /**< REX.B extends the register field in the opcode byte */
128#define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /**< modrm.mod is always 11b */
129#define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
130#define DISOPTYPE_SSE RT_BIT_32(29) /**< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! */
131#define DISOPTYPE_MMX RT_BIT_32(30) /**< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! */
132#define DISOPTYPE_FPU RT_BIT_32(31) /**< FPU instruction. Not implemented yet! */
133#define DISOPTYPE_ALL UINT32_C(0xffffffff)
134/** @} */
135
136/** @name Parameter usage flags.
137 * @{
138 */
139#define DISUSE_BASE RT_BIT_64(0)
140#define DISUSE_INDEX RT_BIT_64(1)
141#define DISUSE_SCALE RT_BIT_64(2)
142#define DISUSE_REG_GEN8 RT_BIT_64(3)
143#define DISUSE_REG_GEN16 RT_BIT_64(4)
144#define DISUSE_REG_GEN32 RT_BIT_64(5)
145#define DISUSE_REG_GEN64 RT_BIT_64(6)
146#define DISUSE_REG_FP RT_BIT_64(7)
147#define DISUSE_REG_MMX RT_BIT_64(8)
148#define DISUSE_REG_XMM RT_BIT_64(9)
149#define DISUSE_REG_YMM RT_BIT_64(10)
150#define DISUSE_REG_CR RT_BIT_64(11)
151#define DISUSE_REG_DBG RT_BIT_64(12)
152#define DISUSE_REG_SEG RT_BIT_64(13)
153#define DISUSE_REG_TEST RT_BIT_64(14)
154#define DISUSE_DISPLACEMENT8 RT_BIT_64(15)
155#define DISUSE_DISPLACEMENT16 RT_BIT_64(16)
156#define DISUSE_DISPLACEMENT32 RT_BIT_64(17)
157#define DISUSE_DISPLACEMENT64 RT_BIT_64(18)
158#define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(19)
159#define DISUSE_IMMEDIATE8 RT_BIT_64(20)
160#define DISUSE_IMMEDIATE8_REL RT_BIT_64(21)
161#define DISUSE_IMMEDIATE16 RT_BIT_64(22)
162#define DISUSE_IMMEDIATE16_REL RT_BIT_64(23)
163#define DISUSE_IMMEDIATE32 RT_BIT_64(24)
164#define DISUSE_IMMEDIATE32_REL RT_BIT_64(25)
165#define DISUSE_IMMEDIATE64 RT_BIT_64(26)
166#define DISUSE_IMMEDIATE64_REL RT_BIT_64(27)
167#define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(28)
168#define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(29)
169#define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(30)
170#define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(31)
171/** DS:ESI */
172#define DISUSE_POINTER_DS_BASED RT_BIT_64(32)
173/** ES:EDI */
174#define DISUSE_POINTER_ES_BASED RT_BIT_64(33)
175#define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(34)
176#define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(35)
177#define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
178
179/** Mask of immediate use flags. */
180#define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
181 | DISUSE_IMMEDIATE16 \
182 | DISUSE_IMMEDIATE32 \
183 | DISUSE_IMMEDIATE64 \
184 | DISUSE_IMMEDIATE8_REL \
185 | DISUSE_IMMEDIATE16_REL \
186 | DISUSE_IMMEDIATE32_REL \
187 | DISUSE_IMMEDIATE64_REL \
188 | DISUSE_IMMEDIATE_ADDR_0_32 \
189 | DISUSE_IMMEDIATE_ADDR_16_32 \
190 | DISUSE_IMMEDIATE_ADDR_0_16 \
191 | DISUSE_IMMEDIATE_ADDR_16_16 \
192 | DISUSE_IMMEDIATE16_SX8 \
193 | DISUSE_IMMEDIATE32_SX8 \
194 | DISUSE_IMMEDIATE64_SX8)
195/** Check if the use flags indicates an effective address. */
196#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
197 & ( DISUSE_BASE \
198 | DISUSE_INDEX \
199 | DISUSE_DISPLACEMENT32 \
200 | DISUSE_DISPLACEMENT64 \
201 | DISUSE_DISPLACEMENT16 \
202 | DISUSE_DISPLACEMENT8 \
203 | DISUSE_RIPDISPLACEMENT32) ))
204/** @} */
205
206/** @name 64-bit general register indexes.
207 * This matches the AMD64 register encoding. It is found used in
208 * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
209 * @note Safe to assume same values as the 16-bit and 32-bit general registers.
210 * @{
211 */
212#define DISGREG_RAX UINT8_C(0)
213#define DISGREG_RCX UINT8_C(1)
214#define DISGREG_RDX UINT8_C(2)
215#define DISGREG_RBX UINT8_C(3)
216#define DISGREG_RSP UINT8_C(4)
217#define DISGREG_RBP UINT8_C(5)
218#define DISGREG_RSI UINT8_C(6)
219#define DISGREG_RDI UINT8_C(7)
220#define DISGREG_R8 UINT8_C(8)
221#define DISGREG_R9 UINT8_C(9)
222#define DISGREG_R10 UINT8_C(10)
223#define DISGREG_R11 UINT8_C(11)
224#define DISGREG_R12 UINT8_C(12)
225#define DISGREG_R13 UINT8_C(13)
226#define DISGREG_R14 UINT8_C(14)
227#define DISGREG_R15 UINT8_C(15)
228/** @} */
229
230/** @name 32-bit general register indexes.
231 * This matches the AMD64 register encoding. It is found used in
232 * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
233 * @note Safe to assume same values as the 16-bit and 64-bit general registers.
234 * @{
235 */
236#define DISGREG_EAX UINT8_C(0)
237#define DISGREG_ECX UINT8_C(1)
238#define DISGREG_EDX UINT8_C(2)
239#define DISGREG_EBX UINT8_C(3)
240#define DISGREG_ESP UINT8_C(4)
241#define DISGREG_EBP UINT8_C(5)
242#define DISGREG_ESI UINT8_C(6)
243#define DISGREG_EDI UINT8_C(7)
244#define DISGREG_R8D UINT8_C(8)
245#define DISGREG_R9D UINT8_C(9)
246#define DISGREG_R10D UINT8_C(10)
247#define DISGREG_R11D UINT8_C(11)
248#define DISGREG_R12D UINT8_C(12)
249#define DISGREG_R13D UINT8_C(13)
250#define DISGREG_R14D UINT8_C(14)
251#define DISGREG_R15D UINT8_C(15)
252/** @} */
253
254/** @name 16-bit general register indexes.
255 * This matches the AMD64 register encoding. It is found used in
256 * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
257 * @note Safe to assume same values as the 32-bit and 64-bit general registers.
258 * @{
259 */
260#define DISGREG_AX UINT8_C(0)
261#define DISGREG_CX UINT8_C(1)
262#define DISGREG_DX UINT8_C(2)
263#define DISGREG_BX UINT8_C(3)
264#define DISGREG_SP UINT8_C(4)
265#define DISGREG_BP UINT8_C(5)
266#define DISGREG_SI UINT8_C(6)
267#define DISGREG_DI UINT8_C(7)
268#define DISGREG_R8W UINT8_C(8)
269#define DISGREG_R9W UINT8_C(9)
270#define DISGREG_R10W UINT8_C(10)
271#define DISGREG_R11W UINT8_C(11)
272#define DISGREG_R12W UINT8_C(12)
273#define DISGREG_R13W UINT8_C(13)
274#define DISGREG_R14W UINT8_C(14)
275#define DISGREG_R15W UINT8_C(15)
276/** @} */
277
278/** @name 8-bit general register indexes.
279 * This mostly (?) matches the AMD64 register encoding. It is found used in
280 * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
281 * @{
282 */
283#define DISGREG_AL UINT8_C(0)
284#define DISGREG_CL UINT8_C(1)
285#define DISGREG_DL UINT8_C(2)
286#define DISGREG_BL UINT8_C(3)
287#define DISGREG_AH UINT8_C(4)
288#define DISGREG_CH UINT8_C(5)
289#define DISGREG_DH UINT8_C(6)
290#define DISGREG_BH UINT8_C(7)
291#define DISGREG_R8B UINT8_C(8)
292#define DISGREG_R9B UINT8_C(9)
293#define DISGREG_R10B UINT8_C(10)
294#define DISGREG_R11B UINT8_C(11)
295#define DISGREG_R12B UINT8_C(12)
296#define DISGREG_R13B UINT8_C(13)
297#define DISGREG_R14B UINT8_C(14)
298#define DISGREG_R15B UINT8_C(15)
299#define DISGREG_SPL UINT8_C(16)
300#define DISGREG_BPL UINT8_C(17)
301#define DISGREG_SIL UINT8_C(18)
302#define DISGREG_DIL UINT8_C(19)
303/** @} */
304
305/** @name Segment registerindexes.
306 * This matches the AMD64 register encoding. It is found used in
307 * DISOPPARAM::Base.idxSegReg.
308 * @{
309 */
310typedef enum
311{
312 DISSELREG_ES = 0,
313 DISSELREG_CS = 1,
314 DISSELREG_SS = 2,
315 DISSELREG_DS = 3,
316 DISSELREG_FS = 4,
317 DISSELREG_GS = 5,
318 /** End of the valid register index values. */
319 DISSELREG_END,
320 /** The usual 32-bit paranoia. */
321 DIS_SEGREG_32BIT_HACK = 0x7fffffff
322} DISSELREG;
323/** @} */
324
325/** @name FPU register indexes.
326 * This matches the AMD64 register encoding. It is found used in
327 * DISOPPARAM::Base.idxFpuReg.
328 * @{
329 */
330#define DISFPREG_ST0 UINT8_C(0)
331#define DISFPREG_ST1 UINT8_C(1)
332#define DISFPREG_ST2 UINT8_C(2)
333#define DISFPREG_ST3 UINT8_C(3)
334#define DISFPREG_ST4 UINT8_C(4)
335#define DISFPREG_ST5 UINT8_C(5)
336#define DISFPREG_ST6 UINT8_C(6)
337#define DISFPREG_ST7 UINT8_C(7)
338/** @} */
339
340/** @name Control register indexes.
341 * This matches the AMD64 register encoding. It is found used in
342 * DISOPPARAM::Base.idxCtrlReg.
343 * @{
344 */
345#define DISCREG_CR0 UINT8_C(0)
346#define DISCREG_CR1 UINT8_C(1)
347#define DISCREG_CR2 UINT8_C(2)
348#define DISCREG_CR3 UINT8_C(3)
349#define DISCREG_CR4 UINT8_C(4)
350#define DISCREG_CR8 UINT8_C(8)
351/** @} */
352
353/** @name Debug register indexes.
354 * This matches the AMD64 register encoding. It is found used in
355 * DISOPPARAM::Base.idxDbgReg.
356 * @{
357 */
358#define DISDREG_DR0 UINT8_C(0)
359#define DISDREG_DR1 UINT8_C(1)
360#define DISDREG_DR2 UINT8_C(2)
361#define DISDREG_DR3 UINT8_C(3)
362#define DISDREG_DR4 UINT8_C(4)
363#define DISDREG_DR5 UINT8_C(5)
364#define DISDREG_DR6 UINT8_C(6)
365#define DISDREG_DR7 UINT8_C(7)
366/** @} */
367
368/** @name MMX register indexes.
369 * This matches the AMD64 register encoding. It is found used in
370 * DISOPPARAM::Base.idxMmxReg.
371 * @{
372 */
373#define DISMREG_MMX0 UINT8_C(0)
374#define DISMREG_MMX1 UINT8_C(1)
375#define DISMREG_MMX2 UINT8_C(2)
376#define DISMREG_MMX3 UINT8_C(3)
377#define DISMREG_MMX4 UINT8_C(4)
378#define DISMREG_MMX5 UINT8_C(5)
379#define DISMREG_MMX6 UINT8_C(6)
380#define DISMREG_MMX7 UINT8_C(7)
381/** @} */
382
383/** @name SSE register indexes.
384 * This matches the AMD64 register encoding. It is found used in
385 * DISOPPARAM::Base.idxXmmReg.
386 * @{
387 */
388#define DISXREG_XMM0 UINT8_C(0)
389#define DISXREG_XMM1 UINT8_C(1)
390#define DISXREG_XMM2 UINT8_C(2)
391#define DISXREG_XMM3 UINT8_C(3)
392#define DISXREG_XMM4 UINT8_C(4)
393#define DISXREG_XMM5 UINT8_C(5)
394#define DISXREG_XMM6 UINT8_C(6)
395#define DISXREG_XMM7 UINT8_C(7)
396/** @} */
397
398
399/**
400 * Opcode parameter (operand) details.
401 */
402typedef struct DISOPPARAM
403{
404 /** A combination of DISUSE_XXX. */
405 uint64_t fUse;
406 /** Immediate value or address, applicable if any of the flags included in
407 * DISUSE_IMMEDIATE are set in fUse. */
408 uint64_t uValue;
409 /** Disposition. */
410 union
411 {
412 /** 64-bit displacement, applicable if DISUSE_DISPLACEMENT64 is set in fUse. */
413 int64_t i64;
414 uint64_t u64;
415 /** 32-bit displacement, applicable if DISUSE_DISPLACEMENT32 or
416 * DISUSE_RIPDISPLACEMENT32 is set in fUse. */
417 int32_t i32;
418 uint32_t u32;
419 /** 16-bit displacement, applicable if DISUSE_DISPLACEMENT16 is set in fUse. */
420 int32_t i16;
421 uint32_t u16;
422 /** 8-bit displacement, applicable if DISUSE_DISPLACEMENT8 is set in fUse. */
423 int32_t i8;
424 uint32_t u8;
425 } uDisp;
426 /** The base register from ModR/M or SIB, applicable if DISUSE_BASE is
427 * set in fUse. */
428 union
429 {
430 /** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
431 * DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
432 uint8_t idxGenReg;
433 /** FPU stack register index (DISFPREG_XXX), applicable if DISUSE_REG_FP is
434 * set in fUse. 1:1 indexes. */
435 uint8_t idxFpuReg;
436 /** MMX register index (DISMREG_XXX), applicable if DISUSE_REG_MMX is
437 * set in fUse. 1:1 indexes. */
438 uint8_t idxMmxReg;
439 /** SSE register index (DISXREG_XXX), applicable if DISUSE_REG_XMM is
440 * set in fUse. 1:1 indexes. */
441 uint8_t idxXmmReg;
442 /** SSE2 register index (DISYREG_XXX), applicable if DISUSE_REG_YMM is
443 * set in fUse. 1:1 indexes. */
444 uint8_t idxYmmReg;
445 /** Segment register index (DISSELREG_XXX), applicable if DISUSE_REG_SEG is
446 * set in fUse. */
447 uint8_t idxSegReg;
448 /** Test register, TR0-TR7, present on early IA32 CPUs, applicable if
449 * DISUSE_REG_TEST is set in fUse. No index defines for these. */
450 uint8_t idxTestReg;
451 /** Control register index (DISCREG_XXX), applicable if DISUSE_REG_CR is
452 * set in fUse. 1:1 indexes. */
453 uint8_t idxCtrlReg;
454 /** Debug register index (DISDREG_XXX), applicable if DISUSE_REG_DBG is
455 * set in fUse. 1:1 indexes. */
456 uint8_t idxDbgReg;
457 } Base;
458 /** The SIB index register meaning, applicable if DISUSE_INDEX is
459 * set in fUse. */
460 union
461 {
462 /** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
463 * DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
464 uint8_t idxGenReg;
465 /** XMM register index (DISXREG_XXX), applicable if DISUSE_REG_XMM
466 * is set in fUse. */
467 uint8_t idxXmmReg;
468 /** YMM register index (DISXREG_XXX), applicable if DISUSE_REG_YMM
469 * is set in fUse. */
470 uint8_t idxYmmReg;
471 } Index;
472 /** 2, 4 or 8, if DISUSE_SCALE is set in fUse. */
473 uint8_t uScale;
474 /** Parameter size. */
475 uint8_t cb;
476 /** Copy of the corresponding DISOPCODE::fParam1 / DISOPCODE::fParam2 /
477 * DISOPCODE::fParam3. */
478 uint32_t fParam;
479} DISOPPARAM;
480AssertCompileSize(DISOPPARAM, 32);
481/** Pointer to opcode parameter. */
482typedef DISOPPARAM *PDISOPPARAM;
483/** Pointer to opcode parameter. */
484typedef const DISOPPARAM *PCDISOPPARAM;
485
486
487/**
488 * Opcode descriptor.
489 */
490typedef struct DISOPCODE
491{
492#ifndef DIS_CORE_ONLY
493 const char *pszOpcode;
494#endif
495 /** Parameter \#1 parser index. */
496 uint8_t idxParse1;
497 /** Parameter \#2 parser index. */
498 uint8_t idxParse2;
499 /** Parameter \#3 parser index. */
500 uint8_t idxParse3;
501 /** Parameter \#4 parser index. */
502 uint8_t idxParse4;
503 /** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
504 * VBox/disopcode.h. */
505 uint16_t uOpcode;
506 /** Parameter \#1 info, @see grp_dis_opparam. */
507 uint16_t fParam1;
508 /** Parameter \#2 info, @see grp_dis_opparam. */
509 uint16_t fParam2;
510 /** Parameter \#3 info, @see grp_dis_opparam. */
511 uint16_t fParam3;
512 /** Parameter \#4 info, @see grp_dis_opparam. */
513 uint16_t fParam4;
514 /** padding unused */
515 uint16_t uPadding;
516 /** Operand type flags, DISOPTYPE_XXX. */
517 uint32_t fOpType;
518} DISOPCODE;
519/** Pointer to const opcode. */
520typedef const struct DISOPCODE *PCDISOPCODE;
521
522
523/**
524 * Callback for reading instruction bytes.
525 *
526 * @returns VBox status code, bytes in DISSTATE::abInstr and byte count in
527 * DISSTATE::cbCachedInstr.
528 * @param pDis Pointer to the disassembler state. The user
529 * argument can be found in DISSTATE::pvUser if needed.
530 * @param offInstr The offset relative to the start of the instruction.
531 *
532 * To get the source address, add this to
533 * DISSTATE::uInstrAddr.
534 *
535 * To calculate the destination buffer address, use it
536 * as an index into DISSTATE::abInstr.
537 *
538 * @param cbMinRead The minimum number of bytes to read.
539 * @param cbMaxRead The maximum number of bytes that may be read.
540 */
541typedef DECLCALLBACKTYPE(int, FNDISREADBYTES,(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead));
542/** Pointer to a opcode byte reader. */
543typedef FNDISREADBYTES *PFNDISREADBYTES;
544
545/** Parser callback.
546 * @remark no DECLCALLBACK() here because it's considered to be internal and
547 * there is no point in enforcing CDECL. */
548typedef size_t FNDISPARSE(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam);
549/** Pointer to a disassembler parser function. */
550typedef FNDISPARSE *PFNDISPARSE;
551/** Pointer to a const disassembler parser function pointer. */
552typedef PFNDISPARSE const *PCPFNDISPARSE;
553
554/**
555 * The diassembler state and result.
556 */
557typedef struct DISSTATE
558{
559 /** The number of valid bytes in abInstr. */
560 uint8_t cbCachedInstr;
561 /** SIB fields. */
562 union
563 {
564 /** Bitfield view */
565 struct
566 {
567 uint8_t Base;
568 uint8_t Index;
569 uint8_t Scale;
570 } Bits;
571 } SIB;
572 /** ModRM fields. */
573 union
574 {
575 /** Bitfield view */
576 struct
577 {
578 uint8_t Rm;
579 uint8_t Reg;
580 uint8_t Mod;
581 } Bits;
582 } ModRM;
583 /** The CPU mode (DISCPUMODE). */
584 uint8_t uCpuMode;
585 /** The addressing mode (DISCPUMODE). */
586 uint8_t uAddrMode;
587 /** The operand mode (DISCPUMODE). */
588 uint8_t uOpMode;
589 /** Per instruction prefix settings. */
590 uint8_t fPrefix;
591 /** REX prefix value (64 bits only). */
592 uint8_t fRexPrefix;
593 /** Segment prefix value (DISSELREG). */
594 uint8_t idxSegPrefix;
595 /** Last prefix byte (for SSE2 extension tables). */
596 uint8_t bLastPrefix;
597 /** Last significant opcode byte of instruction. */
598 uint8_t bOpCode;
599 /** The size of the prefix bytes. */
600 uint8_t cbPrefix;
601 /** The instruction size. */
602 uint8_t cbInstr;
603 /** VEX presence flag, destination register and size */
604 uint8_t bVexDestReg;
605 /** VEX.W flag */
606 uint8_t bVexWFlag;
607 /** Unused bytes. */
608 uint8_t abUnused[1];
609 /** Internal: instruction filter */
610 uint32_t fFilter;
611 /** Internal: pointer to disassembly function table */
612 PCPFNDISPARSE pfnDisasmFnTable;
613#if ARCH_BITS == 32
614 uint32_t uPtrPadding1;
615#endif
616 /** Pointer to the current instruction. */
617 PCDISOPCODE pCurInstr;
618#if ARCH_BITS == 32
619 uint32_t uPtrPadding2;
620#endif
621 /** The instruction bytes. */
622 uint8_t abInstr[16];
623 /** SIB displacment. */
624 int32_t i32SibDisp;
625
626 /** Return code set by a worker function like the opcode bytes readers. */
627 int32_t rc;
628 /** The address of the instruction. */
629 RTUINTPTR uInstrAddr;
630 /** Optional read function */
631 PFNDISREADBYTES pfnReadBytes;
632#if ARCH_BITS == 32
633 uint32_t uPadding3;
634#endif
635 /** User data supplied as an argument to the APIs. */
636 void *pvUser;
637#if ARCH_BITS == 32
638 uint32_t uPadding4;
639#endif
640 /** Parameters. */
641 DISOPPARAM Param1;
642 DISOPPARAM Param2;
643 DISOPPARAM Param3;
644 DISOPPARAM Param4;
645} DISSTATE;
646AssertCompileSize(DISSTATE, 0xd8);
647
648/** @deprecated Use DISSTATE and change Cpu and DisState to Dis. */
649typedef DISSTATE DISCPUSTATE;
650
651
652
653DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
654 PDISSTATE pDis, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
655DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
656 PDISSTATE pDis, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
657DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
658 PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
659 PDISSTATE pDis, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
660
661DISDECL(int) DISInstr(void const *pvInstr, DISCPUMODE enmCpuMode, PDISSTATE pDis, uint32_t *pcbInstr);
662DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
663 PDISSTATE pDis, uint32_t *pcbInstr);
664DISDECL(int) DISInstrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
665 PFNDISREADBYTES pfnReadBytes, void *pvUser,
666 PDISSTATE pDis, uint32_t *pcbInstr);
667DISDECL(int) DISInstrWithPrefetchedBytes(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t fFilter,
668 void const *pvPrefetched, size_t cbPretched,
669 PFNDISREADBYTES pfnReadBytes, void *pvUser,
670 PDISSTATE pDis, uint32_t *pcbInstr);
671
672DISDECL(int) DISGetParamSize(PCDISSTATE pDis, PCDISOPPARAM pParam);
673DISDECL(DISSELREG) DISDetectSegReg(PCDISSTATE pDis, PCDISOPPARAM pParam);
674DISDECL(uint8_t) DISQuerySegPrefixByte(PCDISSTATE pDis);
675
676
677
678/** @name Flags returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
679 * @{
680 */
681#define DISQPV_FLAG_8 UINT8_C(0x01)
682#define DISQPV_FLAG_16 UINT8_C(0x02)
683#define DISQPV_FLAG_32 UINT8_C(0x04)
684#define DISQPV_FLAG_64 UINT8_C(0x08)
685#define DISQPV_FLAG_FARPTR16 UINT8_C(0x10)
686#define DISQPV_FLAG_FARPTR32 UINT8_C(0x20)
687/** @} */
688
689/** @name Types returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
690 * @{ */
691#define DISQPV_TYPE_REGISTER UINT8_C(1)
692#define DISQPV_TYPE_ADDRESS UINT8_C(2)
693#define DISQPV_TYPE_IMMEDIATE UINT8_C(3)
694/** @} */
695
696typedef struct
697{
698 union
699 {
700 uint8_t val8;
701 uint16_t val16;
702 uint32_t val32;
703 uint64_t val64;
704
705 struct
706 {
707 uint16_t sel;
708 uint32_t offset;
709 } farptr;
710 } val;
711
712 uint8_t type;
713 uint8_t size;
714 uint8_t flags;
715} DISQPVPARAMVAL;
716/** Pointer to opcode parameter value. */
717typedef DISQPVPARAMVAL *PDISQPVPARAMVAL;
718
719/** Indicates which parameter DISQueryParamVal should operate on. */
720typedef enum DISQPVWHICH
721{
722 DISQPVWHICH_DST = 1,
723 DISQPVWHICH_SRC,
724 DISQPVWHAT_32_BIT_HACK = 0x7fffffff
725} DISQPVWHICH;
726DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype);
727DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, void **ppReg, size_t *pcbSize);
728
729DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
730DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
731DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
732DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
733DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
734DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg);
735DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
736DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
737DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
738DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
739DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
740DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
741DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
742DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
743DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
744
745
746/**
747 * Try resolve an address into a symbol name.
748 *
749 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
750 *
751 * @returns VBox status code.
752 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
753 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
754 * content of pszBuf is truncated and zero terminated.
755 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
756 *
757 * @param pDis Pointer to the disassembler CPU state.
758 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
759 * DIS_FMT_SEL_GET_REG to access this.
760 * @param uAddress The segment address.
761 * @param pszBuf Where to store the symbol name
762 * @param cchBuf The size of the buffer.
763 * @param poff If not a perfect match, then this is where the offset from the return
764 * symbol to the specified address is returned.
765 * @param pvUser The user argument.
766 */
767typedef DECLCALLBACKTYPE(int, FNDISGETSYMBOL,(PCDISSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf,
768 RTINTPTR *poff, void *pvUser));
769/** Pointer to a FNDISGETSYMBOL(). */
770typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
771
772/**
773 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
774 */
775#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
776
777/**
778 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
779 * @returns Selector value.
780 */
781#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
782
783/**
784 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
785 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
786 */
787#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
788
789/** @internal */
790#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
791/** @internal */
792#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
793
794
795/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
796 * @{
797 */
798/** Put the address to the right. */
799#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
800/** Put the address to the left. */
801#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
802/** Put the address in comments.
803 * For some assemblers this implies placing it to the right. */
804#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
805/** Put the instruction bytes to the right of the disassembly. */
806#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
807/** Put the instruction bytes to the left of the disassembly. */
808#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
809/** Put the instruction bytes in comments.
810 * For some assemblers this implies placing the bytes to the right. */
811#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
812/** Put the bytes in square brackets. */
813#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
814/** Put spaces between the bytes. */
815#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
816/** Display the relative +/- offset of branch instructions that uses relative addresses,
817 * and put the target address in parenthesis. */
818#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
819/** Strict assembly. The assembly should, when ever possible, make the
820 * assembler reproduce the exact same binary. (Refers to the yasm
821 * strict keyword.) */
822#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
823/** Checks if the given flags are a valid combination. */
824#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
825 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
826 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
827 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
828 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
829 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
830 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
831 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
832 )
833/** @} */
834
835DISDECL(size_t) DISFormatYasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
836DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
837DISDECL(size_t) DISFormatMasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
838DISDECL(size_t) DISFormatMasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
839DISDECL(size_t) DISFormatGas( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
840DISDECL(size_t) DISFormatGasEx( PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
841
842/** @todo DISAnnotate(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, register
843 * reader, memory reader); */
844
845DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis);
846
847/** @} */
848
849RT_C_DECLS_END
850
851#endif /* !VBOX_INCLUDED_dis_h */
852
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