VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 7109

Last change on this file since 7109 was 7015, checked in by vboxsync, 17 years ago

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1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 */
25
26#ifndef ___VBox_disasm_h
27#define ___VBox_disasm_h
28
29#include <VBox/cdefs.h>
30#include <VBox/types.h>
31#include <VBox/cpum.h>
32#include <VBox/disopcode.h>
33
34#if defined(__L4ENV__)
35#include <setjmp.h>
36#endif
37
38__BEGIN_DECLS
39
40
41/** CPU mode flags (DISCPUSTATE::mode).
42 * @{
43 */
44typedef enum
45{
46 CPUMODE_16BIT = 1,
47 CPUMODE_32BIT = 2,
48 CPUMODE_64BIT = 3,
49 /** hack forcing the size of the enum to 32-bits. */
50 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
51} DISCPUMODE;
52/** @} */
53
54/** Prefix byte flags
55 * @{
56 */
57#define PREFIX_NONE 0
58/** non-default address size. */
59#define PREFIX_ADDRSIZE 1
60/** non-default operand size. */
61#define PREFIX_OPSIZE 2
62/** lock prefix. */
63#define PREFIX_LOCK 4
64/** segment prefix. */
65#define PREFIX_SEG 8
66/** rep(e) prefix (not a prefix, but we'll treat is as one). */
67#define PREFIX_REP 16
68/** rep(e) prefix (not a prefix, but we'll treat is as one). */
69#define PREFIX_REPNE 32
70/** REX prefix (64 bits) */
71#define PREFIX_REX 64
72/** @} */
73
74/** 64 bits prefix byte flags
75 * @{
76 */
77#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_REX)
78#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_REX)
79#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_REX_B)
80#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_REX_X)
81#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_REX_XB)
82#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_REX_R)
83#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_REX_RB)
84#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_REX_RX)
85#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_REX_RXB)
86#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_REX_W)
87#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_REX_WB)
88#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_REX_WX)
89#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_REX_WXB)
90#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_REX_WR)
91#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_REX_WRB)
92#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_REX_WRX)
93#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_REX_WRXB)
94/** @} */
95
96/**
97 * Operand type.
98 */
99#define OPTYPE_INVALID RT_BIT(0)
100#define OPTYPE_HARMLESS RT_BIT(1)
101#define OPTYPE_CONTROLFLOW RT_BIT(2)
102#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
103#define OPTYPE_DANGEROUS RT_BIT(4)
104#define OPTYPE_PORTIO RT_BIT(5)
105#define OPTYPE_PRIVILEGED RT_BIT(6)
106#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
107#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
108#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
109#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
110#define OPTYPE_INTERRUPT RT_BIT(11)
111#define OPTYPE_ILLEGAL RT_BIT(12)
112#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
113#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
114#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
115#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
116#define OPTYPE_PORTIO_READ RT_BIT(17)
117#define OPTYPE_PORTIO_WRITE RT_BIT(18)
118#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
119#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
120#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
121#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
122#define OPTYPE_ALL (0xffffffff)
123
124/** Parameter usage flags.
125 * @{
126 */
127#define USE_BASE RT_BIT(0)
128#define USE_INDEX RT_BIT(1)
129#define USE_SCALE RT_BIT(2)
130#define USE_REG_GEN8 RT_BIT(3)
131#define USE_REG_GEN16 RT_BIT(4)
132#define USE_REG_GEN32 RT_BIT(5)
133#define USE_REG_FP RT_BIT(6)
134#define USE_REG_MMX RT_BIT(7)
135#define USE_REG_XMM RT_BIT(8)
136#define USE_REG_CR RT_BIT(9)
137#define USE_REG_DBG RT_BIT(10)
138#define USE_REG_SEG RT_BIT(11)
139#define USE_REG_TEST RT_BIT(12)
140#define USE_DISPLACEMENT8 RT_BIT(13)
141#define USE_DISPLACEMENT16 RT_BIT(14)
142#define USE_DISPLACEMENT32 RT_BIT(15)
143#define USE_IMMEDIATE8 RT_BIT(16)
144#define USE_IMMEDIATE8_REL RT_BIT(17)
145#define USE_IMMEDIATE16 RT_BIT(18)
146#define USE_IMMEDIATE16_REL RT_BIT(19)
147#define USE_IMMEDIATE32 RT_BIT(20)
148#define USE_IMMEDIATE32_REL RT_BIT(21)
149#define USE_IMMEDIATE64 RT_BIT(22)
150#define USE_IMMEDIATE_ADDR_0_32 RT_BIT(23)
151#define USE_IMMEDIATE_ADDR_16_32 RT_BIT(24)
152#define USE_IMMEDIATE_ADDR_0_16 RT_BIT(25)
153#define USE_IMMEDIATE_ADDR_16_16 RT_BIT(26)
154/** DS:ESI */
155#define USE_POINTER_DS_BASED RT_BIT(27)
156/** ES:EDI */
157#define USE_POINTER_ES_BASED RT_BIT(28)
158#define USE_IMMEDIATE16_SX8 RT_BIT(29)
159#define USE_IMMEDIATE32_SX8 RT_BIT(30)
160
161#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
162
163/** @} */
164
165/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI"}
166 * @{
167 */
168#define USE_REG_EAX 0
169#define USE_REG_ECX 1
170#define USE_REG_EDX 2
171#define USE_REG_EBX 3
172#define USE_REG_ESP 4
173#define USE_REG_EBP 5
174#define USE_REG_ESI 6
175#define USE_REG_EDI 7
176/** @} */
177/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI"}
178 * @{
179 */
180#define USE_REG_AX 0
181#define USE_REG_CX 1
182#define USE_REG_DX 2
183#define USE_REG_BX 3
184#define USE_REG_SP 4
185#define USE_REG_BP 5
186#define USE_REG_SI 6
187#define USE_REG_DI 7
188/** @} */
189
190/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH"}
191 * @{
192 */
193#define USE_REG_AL 0
194#define USE_REG_CL 1
195#define USE_REG_DL 2
196#define USE_REG_BL 3
197#define USE_REG_AH 4
198#define USE_REG_CH 5
199#define USE_REG_DH 6
200#define USE_REG_BH 7
201/** @} */
202
203/** index in {ES, CS, SS, DS, FS, GS}
204 * @{
205 */
206#define USE_REG_ES 0
207#define USE_REG_CS 1
208#define USE_REG_SS 2
209#define USE_REG_DS 3
210#define USE_REG_FS 4
211#define USE_REG_GS 5
212/** @} */
213
214#define USE_REG_FP0 0
215#define USE_REG_FP1 1
216#define USE_REG_FP2 2
217#define USE_REG_FP3 3
218#define USE_REG_FP4 4
219#define USE_REG_FP5 5
220#define USE_REG_FP6 6
221#define USE_REG_FP7 7
222
223#define USE_REG_CR0 0
224#define USE_REG_CR1 1
225#define USE_REG_CR2 2
226#define USE_REG_CR3 3
227#define USE_REG_CR4 4
228
229#define USE_REG_DR0 0
230#define USE_REG_DR1 1
231#define USE_REG_DR2 2
232#define USE_REG_DR3 3
233#define USE_REG_DR4 4
234#define USE_REG_DR5 5
235#define USE_REG_DR6 6
236#define USE_REG_DR7 7
237
238#define USE_REG_MMX0 0
239#define USE_REG_MMX1 1
240#define USE_REG_MMX2 2
241#define USE_REG_MMX3 3
242#define USE_REG_MMX4 4
243#define USE_REG_MMX5 5
244#define USE_REG_MMX6 6
245#define USE_REG_MMX7 7
246
247#define USE_REG_XMM0 0
248#define USE_REG_XMM1 1
249#define USE_REG_XMM2 2
250#define USE_REG_XMM3 3
251#define USE_REG_XMM4 4
252#define USE_REG_XMM5 5
253#define USE_REG_XMM6 6
254#define USE_REG_XMM7 7
255
256/** Used by DISQueryParamVal & EMIQueryParamVal
257 * @{
258 */
259#define PARAM_VAL8 RT_BIT(0)
260#define PARAM_VAL16 RT_BIT(1)
261#define PARAM_VAL32 RT_BIT(2)
262#define PARAM_VAL64 RT_BIT(3)
263#define PARAM_VALFARPTR16 RT_BIT(4)
264#define PARAM_VALFARPTR32 RT_BIT(5)
265
266#define PARMTYPE_REGISTER 1
267#define PARMTYPE_ADDRESS 2
268#define PARMTYPE_IMMEDIATE 3
269
270typedef struct
271{
272 uint32_t type;
273 uint32_t flags;
274 uint32_t size;
275
276 union
277 {
278 uint8_t val8;
279 uint16_t val16;
280 uint32_t val32;
281 uint64_t val64;
282
283 struct
284 {
285 uint16_t sel;
286 uint32_t offset;
287 } farptr;
288 } val;
289
290} OP_PARAMVAL;
291/** Pointer to opcode parameter value. */
292typedef OP_PARAMVAL *POP_PARAMVAL;
293
294typedef enum
295{
296 PARAM_DEST,
297 PARAM_SOURCE
298} PARAM_TYPE;
299
300/** @} */
301
302/**
303 * Operand Parameter.
304 */
305typedef struct _OP_PARAMETER
306{
307 int param;
308 uint64_t parval;
309 char szParam[32];
310
311 int32_t disp8, disp16, disp32;
312
313 uint32_t flags;
314
315 uint32_t size;
316
317 union
318 {
319 uint32_t reg_gen8;
320 uint32_t reg_gen16;
321 uint32_t reg_gen32;
322 /** ST(0) - ST(7) */
323 uint32_t reg_fp;
324 /** MMX0 - MMX7 */
325 uint32_t reg_mmx;
326 /** XMM0 - XMM7 */
327 uint32_t reg_xmm;
328 /** {ES, CS, SS, DS, FS, GS} */
329 uint32_t reg_seg;
330 /** TR0-TR7 (?) */
331 uint32_t reg_test;
332 /** CR0-CR4 */
333 uint32_t reg_ctrl;
334 /** DR0-DR7 */
335 uint32_t reg_dbg;
336 } base;
337 union
338 {
339 uint32_t reg_gen;
340 } index;
341
342 /** 2, 4 or 8. */
343 uint32_t scale;
344
345} OP_PARAMETER;
346/** Pointer to opcode parameter. */
347typedef OP_PARAMETER *POP_PARAMETER;
348/** Pointer to opcode parameter. */
349typedef const OP_PARAMETER *PCOP_PARAMETER;
350
351
352struct _OPCODE;
353/** Pointer to opcode. */
354typedef struct _OPCODE *POPCODE;
355/** Pointer to const opcode. */
356typedef const struct _OPCODE *PCOPCODE;
357
358typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, uint32_t size, void *pvUserdata);
359typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
360
361/* forward decl */
362struct _DISCPUSTATE;
363/** Pointer to the disassembler CPU state. */
364typedef struct _DISCPUSTATE *PDISCPUSTATE;
365
366/** Parser callback.
367 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
368typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
369typedef FNDISPARSE *PFNDISPARSE;
370
371typedef struct _DISCPUSTATE
372{
373 /* Global setting */
374 DISCPUMODE mode;
375
376 /* Per instruction prefix settings */
377 uint32_t prefix;
378 /** segment prefix value. */
379 uint32_t prefix_seg;
380 /** rex prefix value (64 bits only */
381 uint32_t prefix_rex;
382 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
383 DISCPUMODE addrmode;
384 /** operand mode (16 or 32 bits). (CPUMODE_*) */
385 DISCPUMODE opmode;
386
387 OP_PARAMETER param1;
388 OP_PARAMETER param2;
389 OP_PARAMETER param3;
390
391 /** ModRM byte. */
392 uint32_t ModRM;
393 /** scalar, index, base byte. */
394 uint32_t SIB;
395
396 int32_t disp;
397
398 /** First opcode byte of instruction. */
399 uint8_t opcode;
400 /** Last prefix byte (for SSE2 extension tables) */
401 uint8_t lastprefix;
402 RTUINTPTR opaddr;
403 uint32_t opsize;
404#ifndef DIS_CORE_ONLY
405 /** Opcode format string for current instruction. */
406 const char *pszOpcode;
407#endif
408
409 /** Internal: pointer to disassembly function table */
410 PFNDISPARSE *pfnDisasmFnTable;
411 /** Internal: instruction filter */
412 uint32_t uFilter;
413
414 /** Pointer to the current instruction. */
415 PCOPCODE pCurInstr;
416
417 void *apvUserData[3];
418
419 /** Optional read function */
420 PFN_DIS_READBYTES pfnReadBytes;
421#ifdef __L4ENV__
422 jmp_buf *pJumpBuffer;
423#endif /* __L4ENV__ */
424} DISCPUSTATE;
425
426/** Opcode. */
427#pragma pack(4)
428typedef struct _OPCODE
429{
430#ifndef DIS_CORE_ONLY
431 const char *pszOpcode;
432#endif
433 uint8_t idxParse1;
434 uint8_t idxParse2;
435 uint8_t idxParse3;
436 uint16_t opcode;
437 uint16_t param1;
438 uint16_t param2;
439 uint16_t param3;
440
441 uint32_t optype;
442} OPCODE;
443#pragma pack()
444
445
446/**
447 * Disassembles a code block.
448 *
449 * @returns VBox error code
450 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
451 * set correctly.
452 * @param pvCodeBlock Pointer to the strunction to disassemble.
453 * @param cbMax Maximum number of bytes to disassemble.
454 * @param pcbSize Where to store the size of the instruction.
455 * NULL is allowed.
456 *
457 *
458 * @todo Define output callback.
459 * @todo Using signed integers as sizes is a bit odd. There are still
460 * some GCC warnings about mixing signed and unsigend integers.
461 * @todo Need to extend this interface to include a code address so we
462 * can dissassemble GC code. Perhaps a new function is better...
463 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
464 * This means *pcbSize >= cbMax sometimes.
465 */
466DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
467
468/**
469 * Disassembles one instruction
470 *
471 * @returns VBox error code
472 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
473 * set correctly.
474 * @param pu8Instruction Pointer to the instrunction to disassemble.
475 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
476 * @param pcbSize Where to store the size of the instruction.
477 * NULL is allowed.
478 * @param pszOutput Storage for disassembled instruction
479 *
480 * @todo Define output callback.
481 */
482DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
483
484/**
485 * Disassembles one instruction
486 *
487 * @returns VBox error code
488 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
489 * set correctly.
490 * @param pu8Instruction Pointer to the strunction to disassemble.
491 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
492 * @param pcbSize Where to store the size of the instruction.
493 * NULL is allowed.
494 * @param pszOutput Storage for disassembled instruction
495 * @param uFilter Instruction type filter
496 *
497 * @todo Define output callback.
498 */
499DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
500 char *pszOutput, unsigned uFilter);
501
502/**
503 * Parses one instruction.
504 * The result is found in pCpu.
505 *
506 * @returns VBox error code
507 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
508 * @param InstructionAddr Pointer to the instruction to parse.
509 * @param pcbInstruction Where to store the size of the instruction.
510 * NULL is allowed.
511 */
512DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
513
514/**
515 * Parses one guest instruction.
516 * The result is found in pCpu and pcbInstruction.
517 *
518 * @returns VBox status code.
519 * @param InstructionAddr Address of the instruction to decode. What this means
520 * is left to the pfnReadBytes function.
521 * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
522 * @param pfnReadBytes Callback for reading instruction bytes.
523 * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
524 * @param pCpu Pointer to cpu structure. Will be initialized.
525 * @param pcbInstruction Where to store the size of the instruction.
526 * NULL is allowed.
527 */
528DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
529 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
530
531DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
532DISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
533DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
534
535/**
536 * Returns the value of the parameter in pParam
537 *
538 * @returns VBox error code
539 * @param pCtx Exception structure pointer
540 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
541 * set correctly.
542 * @param pParam Pointer to the parameter to parse
543 * @param pParamVal Pointer to parameter value (OUT)
544 * @param parmtype Parameter type
545 *
546 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
547 *
548 */
549DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
550
551DISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, uint32_t reg8, uint8_t *pVal);
552DISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, uint32_t reg16, uint16_t *pVal);
553DISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, uint32_t reg32, uint32_t *pVal);
554DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL *pVal);
555DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg);
556DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, uint32_t reg8, uint8_t val8);
557DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, uint32_t reg32, uint16_t val16);
558DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, uint32_t reg32, uint32_t val32);
559DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, uint32_t sel, RTSEL val);
560
561__END_DECLS
562
563#endif
564
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