dis.h@ 62855

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1	/** @file
2	* DIS - The VirtualBox Disassembler.
3	*/
4
5	/*
6	* Copyright (C) 2006-2016 Oracle Corporation
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*/
25
26	#ifndef ___VBox_dis_h
27	#define ___VBox_dis_h
28
29	#include <VBox/types.h>
30	#include <VBox/disopcode.h>
31	#include <iprt/assert.h>
32
33
34	RT_C_DECLS_BEGIN
35
36	/** @defgroup grp_dis VBox Disassembler
37	* @{ */
38
39	/** @name Prefix byte flags (DISSTATE::fPrefix).
40	* @{
41	*/
42	#define DISPREFIX_NONE UINT8_C(0x00)
43	/** non-default address size. */
44	#define DISPREFIX_ADDRSIZE UINT8_C(0x01)
45	/** non-default operand size. */
46	#define DISPREFIX_OPSIZE UINT8_C(0x02)
47	/** lock prefix. */
48	#define DISPREFIX_LOCK UINT8_C(0x04)
49	/** segment prefix. */
50	#define DISPREFIX_SEG UINT8_C(0x08)
51	/** rep(e) prefix (not a prefix, but we'll treat is as one). */
52	#define DISPREFIX_REP UINT8_C(0x10)
53	/** rep(e) prefix (not a prefix, but we'll treat is as one). */
54	#define DISPREFIX_REPNE UINT8_C(0x20)
55	/** REX prefix (64 bits) */
56	#define DISPREFIX_REX UINT8_C(0x40)
57	/** @} */
58
59	/** @name VEX.Lvvvv prefix destination register flag.
60	* @{
61	*/
62	#define VEX_LEN256 UINT8_C(0x01)
63	#define VEXREG_IS256B(x) ((x) & VEX_LEN256)
64	/* Convert second byte of VEX prefix to internal format */
65	#define VEX_2B2INT(x) ((((x) >> 2) & 0x1f))
66	#define VEX_HAS_REX_R(x) (!((x) & 0x80))
67
68	#define DISPREFIX_VEX_FLAG_W UINT8_C(0x01)
69	/** @} */
70
71	/** @name 64 bits prefix byte flags (DISSTATE::fRexPrefix).
72	* Requires VBox/disopcode.h.
73	* @{
74	*/
75	#define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
76	/#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX) - 0, which is no flag /
77	#define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
78	#define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
79	#define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
80	#define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
81	#define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
82	#define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
83	#define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
84	#define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
85	#define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
86	#define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
87	#define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
88	#define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
89	#define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
90	#define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
91	#define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
92	/** @} */
93	AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_B));
94	AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_X));
95	AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_W));
96	AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_R));
97
98	/** @name Operand type (DISOPCODE::fOpType).
99	* @{
100	*/
101	#define DISOPTYPE_INVALID RT_BIT_32(0)
102	#define DISOPTYPE_HARMLESS RT_BIT_32(1)
103	#define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
104	#define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
105	#define DISOPTYPE_DANGEROUS RT_BIT_32(4)
106	#define DISOPTYPE_PORTIO RT_BIT_32(5)
107	#define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
108	#define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
109	#define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
110	#define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
111	#define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
112	#define DISOPTYPE_INTERRUPT RT_BIT_32(11)
113	#define DISOPTYPE_ILLEGAL RT_BIT_32(12)
114	#define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /*< Some additional dangerous ones when recompiling raw r0. /
115	#define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /*< Some additional dangerous ones when recompiling 16-bit raw r0. /
116	#define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS \| DISOPTYPE_RRM_DANGEROUS_16)
117	#define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /*< Will or can inhibit irqs (sti, pop ss, mov ss) /
118	#define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
119	#define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
120	#define DISOPTYPE_INVALID_64 RT_BIT_32(19) /*< Invalid in 64 bits mode /
121	#define DISOPTYPE_ONLY_64 RT_BIT_32(20) /*< Only valid in 64 bits mode /
122	#define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /*< Default 64 bits operand size /
123	#define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /*< Forced 64 bits operand size; regardless of prefix bytes /
124	#define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /*< REX.B extends the register field in the opcode byte /
125	#define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /*< modrm.mod is always 11b /
126	#define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /*< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) /
127	#define DISOPTYPE_SSE RT_BIT_32(29) /*< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! /
128	#define DISOPTYPE_MMX RT_BIT_32(30) /*< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! /
129	#define DISOPTYPE_FPU RT_BIT_32(31) /*< FPU instruction. Not implemented yet! /
130	#define DISOPTYPE_ALL UINT32_C(0xffffffff)
131	/** @} */
132
133	/** @name Parameter usage flags.
134	* @{
135	*/
136	#define DISUSE_BASE RT_BIT_64(0)
137	#define DISUSE_INDEX RT_BIT_64(1)
138	#define DISUSE_SCALE RT_BIT_64(2)
139	#define DISUSE_REG_GEN8 RT_BIT_64(3)
140	#define DISUSE_REG_GEN16 RT_BIT_64(4)
141	#define DISUSE_REG_GEN32 RT_BIT_64(5)
142	#define DISUSE_REG_GEN64 RT_BIT_64(6)
143	#define DISUSE_REG_FP RT_BIT_64(7)
144	#define DISUSE_REG_MMX RT_BIT_64(8)
145	#define DISUSE_REG_XMM RT_BIT_64(9)
146	#define DISUSE_REG_YMM RT_BIT_64(10)
147	#define DISUSE_REG_CR RT_BIT_64(11)
148	#define DISUSE_REG_DBG RT_BIT_64(12)
149	#define DISUSE_REG_SEG RT_BIT_64(13)
150	#define DISUSE_REG_TEST RT_BIT_64(14)
151	#define DISUSE_DISPLACEMENT8 RT_BIT_64(15)
152	#define DISUSE_DISPLACEMENT16 RT_BIT_64(16)
153	#define DISUSE_DISPLACEMENT32 RT_BIT_64(17)
154	#define DISUSE_DISPLACEMENT64 RT_BIT_64(18)
155	#define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(19)
156	#define DISUSE_IMMEDIATE8 RT_BIT_64(20)
157	#define DISUSE_IMMEDIATE8_REL RT_BIT_64(21)
158	#define DISUSE_IMMEDIATE16 RT_BIT_64(22)
159	#define DISUSE_IMMEDIATE16_REL RT_BIT_64(23)
160	#define DISUSE_IMMEDIATE32 RT_BIT_64(24)
161	#define DISUSE_IMMEDIATE32_REL RT_BIT_64(25)
162	#define DISUSE_IMMEDIATE64 RT_BIT_64(26)
163	#define DISUSE_IMMEDIATE64_REL RT_BIT_64(27)
164	#define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(28)
165	#define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(29)
166	#define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(30)
167	#define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(31)
168	/** DS:ESI */
169	#define DISUSE_POINTER_DS_BASED RT_BIT_64(32)
170	/** ES:EDI */
171	#define DISUSE_POINTER_ES_BASED RT_BIT_64(33)
172	#define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(34)
173	#define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(35)
174	#define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
175
176	/** Mask of immediate use flags. */
177	#define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
178	\| DISUSE_IMMEDIATE16 \
179	\| DISUSE_IMMEDIATE32 \
180	\| DISUSE_IMMEDIATE64 \
181	\| DISUSE_IMMEDIATE8_REL \
182	\| DISUSE_IMMEDIATE16_REL \
183	\| DISUSE_IMMEDIATE32_REL \
184	\| DISUSE_IMMEDIATE64_REL \
185	\| DISUSE_IMMEDIATE_ADDR_0_32 \
186	\| DISUSE_IMMEDIATE_ADDR_16_32 \
187	\| DISUSE_IMMEDIATE_ADDR_0_16 \
188	\| DISUSE_IMMEDIATE_ADDR_16_16 \
189	\| DISUSE_IMMEDIATE16_SX8 \
190	\| DISUSE_IMMEDIATE32_SX8 \
191	\| DISUSE_IMMEDIATE64_SX8)
192	/** Check if the use flags indicates an effective address. */
193	#define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
194	& ( DISUSE_BASE \
195	\| DISUSE_INDEX \
196	\| DISUSE_DISPLACEMENT32 \
197	\| DISUSE_DISPLACEMENT64 \
198	\| DISUSE_DISPLACEMENT16 \
199	\| DISUSE_DISPLACEMENT8 \
200	\| DISUSE_RIPDISPLACEMENT32) ))
201	/** @} */
202
203	/** @name 64-bit general register indexes.
204	* This matches the AMD64 register encoding. It is found used in
205	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
206	* @note Safe to assume same values as the 16-bit and 32-bit general registers.
207	* @{
208	*/
209	#define DISGREG_RAX UINT8_C(0)
210	#define DISGREG_RCX UINT8_C(1)
211	#define DISGREG_RDX UINT8_C(2)
212	#define DISGREG_RBX UINT8_C(3)
213	#define DISGREG_RSP UINT8_C(4)
214	#define DISGREG_RBP UINT8_C(5)
215	#define DISGREG_RSI UINT8_C(6)
216	#define DISGREG_RDI UINT8_C(7)
217	#define DISGREG_R8 UINT8_C(8)
218	#define DISGREG_R9 UINT8_C(9)
219	#define DISGREG_R10 UINT8_C(10)
220	#define DISGREG_R11 UINT8_C(11)
221	#define DISGREG_R12 UINT8_C(12)
222	#define DISGREG_R13 UINT8_C(13)
223	#define DISGREG_R14 UINT8_C(14)
224	#define DISGREG_R15 UINT8_C(15)
225	/** @} */
226
227	/** @name 32-bit general register indexes.
228	* This matches the AMD64 register encoding. It is found used in
229	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
230	* @note Safe to assume same values as the 16-bit and 64-bit general registers.
231	* @{
232	*/
233	#define DISGREG_EAX UINT8_C(0)
234	#define DISGREG_ECX UINT8_C(1)
235	#define DISGREG_EDX UINT8_C(2)
236	#define DISGREG_EBX UINT8_C(3)
237	#define DISGREG_ESP UINT8_C(4)
238	#define DISGREG_EBP UINT8_C(5)
239	#define DISGREG_ESI UINT8_C(6)
240	#define DISGREG_EDI UINT8_C(7)
241	#define DISGREG_R8D UINT8_C(8)
242	#define DISGREG_R9D UINT8_C(9)
243	#define DISGREG_R10D UINT8_C(10)
244	#define DISGREG_R11D UINT8_C(11)
245	#define DISGREG_R12D UINT8_C(12)
246	#define DISGREG_R13D UINT8_C(13)
247	#define DISGREG_R14D UINT8_C(14)
248	#define DISGREG_R15D UINT8_C(15)
249	/** @} */
250
251	/** @name 16-bit general register indexes.
252	* This matches the AMD64 register encoding. It is found used in
253	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
254	* @note Safe to assume same values as the 32-bit and 64-bit general registers.
255	* @{
256	*/
257	#define DISGREG_AX UINT8_C(0)
258	#define DISGREG_CX UINT8_C(1)
259	#define DISGREG_DX UINT8_C(2)
260	#define DISGREG_BX UINT8_C(3)
261	#define DISGREG_SP UINT8_C(4)
262	#define DISGREG_BP UINT8_C(5)
263	#define DISGREG_SI UINT8_C(6)
264	#define DISGREG_DI UINT8_C(7)
265	#define DISGREG_R8W UINT8_C(8)
266	#define DISGREG_R9W UINT8_C(9)
267	#define DISGREG_R10W UINT8_C(10)
268	#define DISGREG_R11W UINT8_C(11)
269	#define DISGREG_R12W UINT8_C(12)
270	#define DISGREG_R13W UINT8_C(13)
271	#define DISGREG_R14W UINT8_C(14)
272	#define DISGREG_R15W UINT8_C(15)
273	/** @} */
274
275	/** @name 8-bit general register indexes.
276	* This mostly (?) matches the AMD64 register encoding. It is found used in
277	* DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
278	* @{
279	*/
280	#define DISGREG_AL UINT8_C(0)
281	#define DISGREG_CL UINT8_C(1)
282	#define DISGREG_DL UINT8_C(2)
283	#define DISGREG_BL UINT8_C(3)
284	#define DISGREG_AH UINT8_C(4)
285	#define DISGREG_CH UINT8_C(5)
286	#define DISGREG_DH UINT8_C(6)
287	#define DISGREG_BH UINT8_C(7)
288	#define DISGREG_R8B UINT8_C(8)
289	#define DISGREG_R9B UINT8_C(9)
290	#define DISGREG_R10B UINT8_C(10)
291	#define DISGREG_R11B UINT8_C(11)
292	#define DISGREG_R12B UINT8_C(12)
293	#define DISGREG_R13B UINT8_C(13)
294	#define DISGREG_R14B UINT8_C(14)
295	#define DISGREG_R15B UINT8_C(15)
296	#define DISGREG_SPL UINT8_C(16)
297	#define DISGREG_BPL UINT8_C(17)
298	#define DISGREG_SIL UINT8_C(18)
299	#define DISGREG_DIL UINT8_C(19)
300	/** @} */
301
302	/** @name Segment registerindexes.
303	* This matches the AMD64 register encoding. It is found used in
304	* DISOPPARAM::Base.idxSegReg.
305	* @{
306	*/
307	typedef enum
308	{
309	DISSELREG_ES = 0,
310	DISSELREG_CS = 1,
311	DISSELREG_SS = 2,
312	DISSELREG_DS = 3,
313	DISSELREG_FS = 4,
314	DISSELREG_GS = 5,
315	/** End of the valid register index values. */
316	DISSELREG_END,
317	/** The usual 32-bit paranoia. */
318	DIS_SEGREG_32BIT_HACK = 0x7fffffff
319	} DISSELREG;
320	/** @} */
321
322	/** @name FPU register indexes.
323	* This matches the AMD64 register encoding. It is found used in
324	* DISOPPARAM::Base.idxFpuReg.
325	* @{
326	*/
327	#define DISFPREG_ST0 UINT8_C(0)
328	#define DISFPREG_ST1 UINT8_C(1)
329	#define DISFPREG_ST2 UINT8_C(2)
330	#define DISFPREG_ST3 UINT8_C(3)
331	#define DISFPREG_ST4 UINT8_C(4)
332	#define DISFPREG_ST5 UINT8_C(5)
333	#define DISFPREG_ST6 UINT8_C(6)
334	#define DISFPREG_ST7 UINT8_C(7)
335	/** @} */
336
337	/** @name Control register indexes.
338	* This matches the AMD64 register encoding. It is found used in
339	* DISOPPARAM::Base.idxCtrlReg.
340	* @{
341	*/
342	#define DISCREG_CR0 UINT8_C(0)
343	#define DISCREG_CR1 UINT8_C(1)
344	#define DISCREG_CR2 UINT8_C(2)
345	#define DISCREG_CR3 UINT8_C(3)
346	#define DISCREG_CR4 UINT8_C(4)
347	#define DISCREG_CR8 UINT8_C(8)
348	/** @} */
349
350	/** @name Debug register indexes.
351	* This matches the AMD64 register encoding. It is found used in
352	* DISOPPARAM::Base.idxDbgReg.
353	* @{
354	*/
355	#define DISDREG_DR0 UINT8_C(0)
356	#define DISDREG_DR1 UINT8_C(1)
357	#define DISDREG_DR2 UINT8_C(2)
358	#define DISDREG_DR3 UINT8_C(3)
359	#define DISDREG_DR4 UINT8_C(4)
360	#define DISDREG_DR5 UINT8_C(5)
361	#define DISDREG_DR6 UINT8_C(6)
362	#define DISDREG_DR7 UINT8_C(7)
363	/** @} */
364
365	/** @name MMX register indexes.
366	* This matches the AMD64 register encoding. It is found used in
367	* DISOPPARAM::Base.idxMmxReg.
368	* @{
369	*/
370	#define DISMREG_MMX0 UINT8_C(0)
371	#define DISMREG_MMX1 UINT8_C(1)
372	#define DISMREG_MMX2 UINT8_C(2)
373	#define DISMREG_MMX3 UINT8_C(3)
374	#define DISMREG_MMX4 UINT8_C(4)
375	#define DISMREG_MMX5 UINT8_C(5)
376	#define DISMREG_MMX6 UINT8_C(6)
377	#define DISMREG_MMX7 UINT8_C(7)
378	/** @} */
379
380	/** @name SSE register indexes.
381	* This matches the AMD64 register encoding. It is found used in
382	* DISOPPARAM::Base.idxXmmReg.
383	* @{
384	*/
385	#define DISXREG_XMM0 UINT8_C(0)
386	#define DISXREG_XMM1 UINT8_C(1)
387	#define DISXREG_XMM2 UINT8_C(2)
388	#define DISXREG_XMM3 UINT8_C(3)
389	#define DISXREG_XMM4 UINT8_C(4)
390	#define DISXREG_XMM5 UINT8_C(5)
391	#define DISXREG_XMM6 UINT8_C(6)
392	#define DISXREG_XMM7 UINT8_C(7)
393	/** @} */
394
395
396	/**
397	* Opcode parameter (operand) details.
398	*/
399	typedef struct DISOPPARAM
400	{
401	/** A combination of DISUSE_XXX. */
402	uint64_t fUse;
403	/** Immediate value or address, applicable if any of the flags included in
404	* DISUSE_IMMEDIATE are set in fUse. */
405	uint64_t uValue;
406	/** Disposition. */
407	union
408	{
409	/** 64-bit displacement, applicable if DISUSE_DISPLACEMENT64 is set in fUse. */
410	int64_t i64;
411	uint64_t u64;
412	/** 32-bit displacement, applicable if DISUSE_DISPLACEMENT32 or
413	* DISUSE_RIPDISPLACEMENT32 is set in fUse. */
414	int32_t i32;
415	uint32_t u32;
416	/** 16-bit displacement, applicable if DISUSE_DISPLACEMENT16 is set in fUse. */
417	int32_t i16;
418	uint32_t u16;
419	/** 8-bit displacement, applicable if DISUSE_DISPLACEMENT8 is set in fUse. */
420	int32_t i8;
421	uint32_t u8;
422	} uDisp;
423	/** The base register from ModR/M or SIB, applicable if DISUSE_BASE is
424	* set in fUse. */
425	union
426	{
427	/** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
428	* DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
429	uint8_t idxGenReg;
430	/** FPU stack register index (DISFPREG_XXX), applicable if DISUSE_REG_FP is
431	* set in fUse. 1:1 indexes. */
432	uint8_t idxFpuReg;
433	/** MMX register index (DISMREG_XXX), applicable if DISUSE_REG_MMX is
434	* set in fUse. 1:1 indexes. */
435	uint8_t idxMmxReg;
436	/** SSE register index (DISXREG_XXX), applicable if DISUSE_REG_XMM is
437	* set in fUse. 1:1 indexes. */
438	uint8_t idxXmmReg;
439	/** SSE2 register index (DISYREG_XXX), applicable if DISUSE_REG_YMM is
440	* set in fUse. 1:1 indexes. */
441	uint8_t idxYmmReg;
442	/** Segment register index (DISSELREG_XXX), applicable if DISUSE_REG_SEG is
443	* set in fUse. */
444	uint8_t idxSegReg;
445	/** Test register, TR0-TR7, present on early IA32 CPUs, applicable if
446	* DISUSE_REG_TEST is set in fUse. No index defines for these. */
447	uint8_t idxTestReg;
448	/** Control register index (DISCREG_XXX), applicable if DISUSE_REG_CR is
449	* set in fUse. 1:1 indexes. */
450	uint8_t idxCtrlReg;
451	/** Debug register index (DISDREG_XXX), applicable if DISUSE_REG_DBG is
452	* set in fUse. 1:1 indexes. */
453	uint8_t idxDbgReg;
454	} Base;
455	/** The SIB index register meaning, applicable if DISUSE_INDEX is
456	* set in fUse. */
457	union
458	{
459	/** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
460	* DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
461	uint8_t idxGenReg;
462	/** XMM register index (DISXREG_XXX), applicable if DISUSE_REG_XMM
463	* is set in fUse. */
464	uint8_t idxXmmReg;
465	/** YMM register index (DISXREG_XXX), applicable if DISUSE_REG_YMM
466	* is set in fUse. */
467	uint8_t idxYmmReg;
468	} Index;
469	/** 2, 4 or 8, if DISUSE_SCALE is set in fUse. */
470	uint8_t uScale;
471	/** Parameter size. */
472	uint8_t cb;
473	/** Copy of the corresponding DISOPCODE::fParam1 / DISOPCODE::fParam2 /
474	* DISOPCODE::fParam3. */
475	uint32_t fParam;
476	} DISOPPARAM;
477	AssertCompileSize(DISOPPARAM, 32);
478	/** Pointer to opcode parameter. */
479	typedef DISOPPARAM *PDISOPPARAM;
480	/** Pointer to opcode parameter. */
481	typedef const DISOPPARAM *PCDISOPPARAM;
482
483
484	/**
485	* Opcode descriptor.
486	*/
487	typedef struct DISOPCODE
488	{
489	#ifndef DIS_CORE_ONLY
490	const char *pszOpcode;
491	#endif
492	/** Parameter \#1 parser index. */
493	uint8_t idxParse1;
494	/** Parameter \#2 parser index. */
495	uint8_t idxParse2;
496	/** Parameter \#3 parser index. */
497	uint8_t idxParse3;
498	/** Parameter \#4 parser index. */
499	uint8_t idxParse4;
500	/** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
501	* VBox/disopcode.h. */
502	uint16_t uOpcode;
503	/** Parameter \#1 info, @see grp_dis_opparam. */
504	uint16_t fParam1;
505	/** Parameter \#2 info, @see grp_dis_opparam. */
506	uint16_t fParam2;
507	/** Parameter \#3 info, @see grp_dis_opparam. */
508	uint16_t fParam3;
509	/** Parameter \#4 info, @see grp_dis_opparam. */
510	uint16_t fParam4;
511	/** padding unused */
512	uint16_t uPadding;
513	/** Operand type flags, DISOPTYPE_XXX. */
514	uint32_t fOpType;
515	} DISOPCODE;
516	/** Pointer to const opcode. */
517	typedef const struct DISOPCODE *PCDISOPCODE;
518
519
520	/**
521	* Callback for reading instruction bytes.
522	*
523	* @returns VBox status code, bytes in DISSTATE::abInstr and byte count in
524	* DISSTATE::cbCachedInstr.
525	* @param pDis Pointer to the disassembler state. The user
526	* argument can be found in DISSTATE::pvUser if needed.
527	* @param offInstr The offset relative to the start of the instruction.
528	*
529	* To get the source address, add this to
530	* DISSTATE::uInstrAddr.
531	*
532	* To calculate the destination buffer address, use it
533	* as an index into DISSTATE::abInstr.
534	*
535	* @param cbMinRead The minimum number of bytes to read.
536	* @param cbMaxRead The maximum number of bytes that may be read.
537	*/
538	typedef DECLCALLBACK(int) FNDISREADBYTES(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead);
539	/** Pointer to a opcode byte reader. */
540	typedef FNDISREADBYTES *PFNDISREADBYTES;
541
542	/** Parser callback.
543	* @remark no DECLCALLBACK() here because it's considered to be internal and
544	* there is no point in enforcing CDECL. */
545	typedef size_t FNDISPARSE(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam);
546	/** Pointer to a disassembler parser function. */
547	typedef FNDISPARSE *PFNDISPARSE;
548	/** Pointer to a const disassembler parser function pointer. */
549	typedef PFNDISPARSE const *PCPFNDISPARSE;
550
551	/**
552	* The diassembler state and result.
553	*/
554	typedef struct DISSTATE
555	{
556	/** The number of valid bytes in abInstr. */
557	uint8_t cbCachedInstr;
558	/** SIB fields. */
559	union
560	{
561	/** Bitfield view */
562	struct
563	{
564	uint8_t Base;
565	uint8_t Index;
566	uint8_t Scale;
567	} Bits;
568	} SIB;
569	/** ModRM fields. */
570	union
571	{
572	/** Bitfield view */
573	struct
574	{
575	uint8_t Rm;
576	uint8_t Reg;
577	uint8_t Mod;
578	} Bits;
579	} ModRM;
580	/** The CPU mode (DISCPUMODE). */
581	uint8_t uCpuMode;
582	/** The addressing mode (DISCPUMODE). */
583	uint8_t uAddrMode;
584	/** The operand mode (DISCPUMODE). */
585	uint8_t uOpMode;
586	/** Per instruction prefix settings. */
587	uint8_t fPrefix;
588	/** REX prefix value (64 bits only). */
589	uint8_t fRexPrefix;
590	/** Segment prefix value (DISSELREG). */
591	uint8_t idxSegPrefix;
592	/** Last prefix byte (for SSE2 extension tables). */
593	uint8_t bLastPrefix;
594	/** Last significant opcode byte of instruction. */
595	uint8_t bOpCode;
596	/** The size of the prefix bytes. */
597	uint8_t cbPrefix;
598	/** The instruction size. */
599	uint8_t cbInstr;
600	/** VEX presence flag, destination register and size */
601	uint8_t bVexDestReg;
602	/** VEX.W flag */
603	uint8_t bVexWFlag;
604	/** Unused bytes. */
605	uint8_t abUnused[1];
606	/** Internal: instruction filter */
607	uint32_t fFilter;
608	/** Internal: pointer to disassembly function table */
609	PCPFNDISPARSE pfnDisasmFnTable;
610	#if ARCH_BITS == 32
611	uint32_t uPtrPadding1;
612	#endif
613	/** Pointer to the current instruction. */
614	PCDISOPCODE pCurInstr;
615	#if ARCH_BITS == 32
616	uint32_t uPtrPadding2;
617	#endif
618	/** The instruction bytes. */
619	uint8_t abInstr[16];
620	/** SIB displacment. */
621	int32_t i32SibDisp;
622
623	/** Return code set by a worker function like the opcode bytes readers. */
624	int32_t rc;
625	/** The address of the instruction. */
626	RTUINTPTR uInstrAddr;
627	/** Optional read function */
628	PFNDISREADBYTES pfnReadBytes;
629	#if ARCH_BITS == 32
630	uint32_t uPadding3;
631	#endif
632	/** User data supplied as an argument to the APIs. */
633	void *pvUser;
634	#if ARCH_BITS == 32
635	uint32_t uPadding4;
636	#endif
637	/** Parameters. */
638	DISOPPARAM Param1;
639	DISOPPARAM Param2;
640	DISOPPARAM Param3;
641	DISOPPARAM Param4;
642	} DISSTATE;
643	AssertCompileSize(DISSTATE, 0xd8);
644
645	/** @deprecated Use DISSTATE and change Cpu and DisState to Dis. */
646	typedef DISSTATE DISCPUSTATE;
647
648
649
650	DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
651	PDISSTATE pDis, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
652	DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
653	PDISSTATE pDis, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
654	DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
655	PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
656	PDISSTATE pDis, uint32_t pcbInstr, char pszOutput, size_t cbOutput);
657
658	DISDECL(int) DISInstr(void const pvInstr, DISCPUMODE enmCpuMode, PDISSTATE pDis, uint32_t pcbInstr);
659	DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
660	PDISSTATE pDis, uint32_t *pcbInstr);
661	DISDECL(int) DISInstrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
662	PFNDISREADBYTES pfnReadBytes, void *pvUser,
663	PDISSTATE pDis, uint32_t *pcbInstr);
664	DISDECL(int) DISInstrWithPrefetchedBytes(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t fFilter,
665	void const *pvPrefetched, size_t cbPretched,
666	PFNDISREADBYTES pfnReadBytes, void *pvUser,
667	PDISSTATE pDis, uint32_t *pcbInstr);
668
669	DISDECL(int) DISGetParamSize(PCDISSTATE pDis, PCDISOPPARAM pParam);
670	DISDECL(DISSELREG) DISDetectSegReg(PCDISSTATE pDis, PCDISOPPARAM pParam);
671	DISDECL(uint8_t) DISQuerySegPrefixByte(PCDISSTATE pDis);
672
673
674
675	/** @name Flags returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
676	* @{
677	*/
678	#define DISQPV_FLAG_8 UINT8_C(0x01)
679	#define DISQPV_FLAG_16 UINT8_C(0x02)
680	#define DISQPV_FLAG_32 UINT8_C(0x04)
681	#define DISQPV_FLAG_64 UINT8_C(0x08)
682	#define DISQPV_FLAG_FARPTR16 UINT8_C(0x10)
683	#define DISQPV_FLAG_FARPTR32 UINT8_C(0x20)
684	/** @} */
685
686	/** @name Types returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
687	* @{ */
688	#define DISQPV_TYPE_REGISTER UINT8_C(1)
689	#define DISQPV_TYPE_ADDRESS UINT8_C(2)
690	#define DISQPV_TYPE_IMMEDIATE UINT8_C(3)
691	/** @} */
692
693	typedef struct
694	{
695	union
696	{
697	uint8_t val8;
698	uint16_t val16;
699	uint32_t val32;
700	uint64_t val64;
701
702	struct
703	{
704	uint16_t sel;
705	uint32_t offset;
706	} farptr;
707	} val;
708
709	uint8_t type;
710	uint8_t size;
711	uint8_t flags;
712	} DISQPVPARAMVAL;
713	/** Pointer to opcode parameter value. */
714	typedef DISQPVPARAMVAL *PDISQPVPARAMVAL;
715
716	/** Indicates which parameter DISQueryParamVal should operate on. */
717	typedef enum DISQPVWHICH
718	{
719	DISQPVWHICH_DST = 1,
720	DISQPVWHICH_SRC,
721	DISQPVWHAT_32_BIT_HACK = 0x7fffffff
722	} DISQPVWHICH;
723	DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype);
724	DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, void *ppReg, size_t pcbSize);
725
726	DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
727	DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
728	DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
729	DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
730	DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
731	DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg);
732	DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
733	DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
734	DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
735	DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
736	DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
737	DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
738	DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
739	DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
740	DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
741
742
743	/**
744	* Try resolve an address into a symbol name.
745	*
746	* For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
747	*
748	* @returns VBox status code.
749	* @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
750	* @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
751	* content of pszBuf is truncated and zero terminated.
752	* @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
753	*
754	* @param pDis Pointer to the disassembler CPU state.
755	* @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
756	* DIS_FMT_SEL_GET_REG to access this.
757	* @param uAddress The segment address.
758	* @param pszBuf Where to store the symbol name
759	* @param cchBuf The size of the buffer.
760	* @param poff If not a perfect match, then this is where the offset from the return
761	* symbol to the specified address is returned.
762	* @param pvUser The user argument.
763	*/
764	typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser);
765	/** Pointer to a FNDISGETSYMBOL(). */
766	typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
767
768	/**
769	* Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
770	*/
771	#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
772
773	/**
774	* Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
775	* @returns Selector value.
776	*/
777	#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
778
779	/**
780	* Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
781	* @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
782	*/
783	#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
784
785	/** @internal */
786	#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) \| RT_BIT(31) \| 0xffff )
787	/** @internal */
788	#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
789
790
791	/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
792	* @{
793	*/
794	/** Put the address to the right. */
795	#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
796	/** Put the address to the left. */
797	#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
798	/** Put the address in comments.
799	* For some assemblers this implies placing it to the right. */
800	#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
801	/** Put the instruction bytes to the right of the disassembly. */
802	#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
803	/** Put the instruction bytes to the left of the disassembly. */
804	#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
805	/** Put the instruction bytes in comments.
806	* For some assemblers this implies placing the bytes to the right. */
807	#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
808	/** Put the bytes in square brackets. */
809	#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
810	/** Put spaces between the bytes. */
811	#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
812	/** Display the relative +/- offset of branch instructions that uses relative addresses,
813	* and put the target address in parenthesis. */
814	#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
815	/** Strict assembly. The assembly should, when ever possible, make the
816	* assembler reproduce the exact same binary. (Refers to the yasm
817	* strict keyword.) */
818	#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
819	/** Checks if the given flags are a valid combination. */
820	#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
821	( !((fFlags) & ~UINT32_C(0x000003ff)) \
822	&& ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT) \
823	&& ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
824	\|\| (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT \| DIS_FMT_FLAGS_ADDR_LEFT)) ) \
825	&& ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT) \
826	&& ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT \| DIS_FMT_FLAGS_BYTES_BRACKETS)) \
827	\|\| (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT \| DIS_FMT_FLAGS_BYTES_LEFT)) ) \
828	)
829	/** @} */
830
831	DISDECL(size_t) DISFormatYasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
832	DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
833	DISDECL(size_t) DISFormatMasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
834	DISDECL(size_t) DISFormatMasmEx(PCDISSTATE pDis, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
835	DISDECL(size_t) DISFormatGas( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
836	DISDECL(size_t) DISFormatGasEx( PCDISSTATE pDis, char pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void pvUser);
837
838	/** @todo DISAnnotate(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, register
839	* reader, memory reader); */
840
841	DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis);
842
843	/** @} */
844
845	RT_C_DECLS_END
846
847	#endif
848

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source: vbox/trunk/include/VBox/dis.h@ 62855

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