VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 10107

Last change on this file since 10107 was 10107, checked in by vboxsync, 16 years ago

Added CR8 write (alias for APIC TPR write).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 29.0 KB
Line 
1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_disasm_h
31#define ___VBox_disasm_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/disopcode.h>
36
37#if defined(__L4ENV__)
38#include <setjmp.h>
39#endif
40
41__BEGIN_DECLS
42
43
44/** CPU mode flags (DISCPUSTATE::mode).
45 * @{
46 */
47typedef enum
48{
49 CPUMODE_16BIT = 1,
50 CPUMODE_32BIT = 2,
51 CPUMODE_64BIT = 3,
52 /** hack forcing the size of the enum to 32-bits. */
53 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
54} DISCPUMODE;
55/** @} */
56
57/** Prefix byte flags
58 * @{
59 */
60#define PREFIX_NONE 0
61/** non-default address size. */
62#define PREFIX_ADDRSIZE RT_BIT(0)
63/** non-default operand size. */
64#define PREFIX_OPSIZE RT_BIT(1)
65/** lock prefix. */
66#define PREFIX_LOCK RT_BIT(2)
67/** segment prefix. */
68#define PREFIX_SEG RT_BIT(3)
69/** rep(e) prefix (not a prefix, but we'll treat is as one). */
70#define PREFIX_REP RT_BIT(4)
71/** rep(e) prefix (not a prefix, but we'll treat is as one). */
72#define PREFIX_REPNE RT_BIT(5)
73/** REX prefix (64 bits) */
74#define PREFIX_REX RT_BIT(6)
75/** @} */
76
77/** 64 bits prefix byte flags
78 * @{
79 */
80#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
81#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
82#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
83#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
84#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
85#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
86#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
87#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
88#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
89#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
90#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
91#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
92#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
93#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
94#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
95#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
96#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
97/** @} */
98
99/**
100 * Operand type.
101 */
102#define OPTYPE_INVALID RT_BIT(0)
103#define OPTYPE_HARMLESS RT_BIT(1)
104#define OPTYPE_CONTROLFLOW RT_BIT(2)
105#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
106#define OPTYPE_DANGEROUS RT_BIT(4)
107#define OPTYPE_PORTIO RT_BIT(5)
108#define OPTYPE_PRIVILEGED RT_BIT(6)
109#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
110#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
111#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
112#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
113#define OPTYPE_INTERRUPT RT_BIT(11)
114#define OPTYPE_ILLEGAL RT_BIT(12)
115#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
116#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
117#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
118#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
119#define OPTYPE_PORTIO_READ RT_BIT(17)
120#define OPTYPE_PORTIO_WRITE RT_BIT(18)
121#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
122#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
123#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
124#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
125#define OPTYPE_REXB_EXTENDS_OPREG RT_BIT(23) /**< REX.B extends the register field in the opcode byte */
126#define OPTYPE_ALL (0xffffffff)
127
128/** Parameter usage flags.
129 * @{
130 */
131#define USE_BASE RT_BIT_64(0)
132#define USE_INDEX RT_BIT_64(1)
133#define USE_SCALE RT_BIT_64(2)
134#define USE_REG_GEN8 RT_BIT_64(3)
135#define USE_REG_GEN16 RT_BIT_64(4)
136#define USE_REG_GEN32 RT_BIT_64(5)
137#define USE_REG_GEN64 RT_BIT_64(6)
138#define USE_REG_FP RT_BIT_64(7)
139#define USE_REG_MMX RT_BIT_64(8)
140#define USE_REG_XMM RT_BIT_64(9)
141#define USE_REG_CR RT_BIT_64(10)
142#define USE_REG_DBG RT_BIT_64(11)
143#define USE_REG_SEG RT_BIT_64(12)
144#define USE_REG_TEST RT_BIT_64(13)
145#define USE_DISPLACEMENT8 RT_BIT_64(14)
146#define USE_DISPLACEMENT16 RT_BIT_64(15)
147#define USE_DISPLACEMENT32 RT_BIT_64(16)
148#define USE_DISPLACEMENT64 RT_BIT_64(17)
149#define USE_RIPDISPLACEMENT32 RT_BIT_64(18)
150#define USE_IMMEDIATE8 RT_BIT_64(19)
151#define USE_IMMEDIATE8_REL RT_BIT_64(20)
152#define USE_IMMEDIATE16 RT_BIT_64(21)
153#define USE_IMMEDIATE16_REL RT_BIT_64(22)
154#define USE_IMMEDIATE32 RT_BIT_64(23)
155#define USE_IMMEDIATE32_REL RT_BIT_64(24)
156#define USE_IMMEDIATE64 RT_BIT_64(25)
157#define USE_IMMEDIATE64_REL RT_BIT_64(26)
158#define USE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
159#define USE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
160#define USE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
161#define USE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
162/** DS:ESI */
163#define USE_POINTER_DS_BASED RT_BIT_64(31)
164/** ES:EDI */
165#define USE_POINTER_ES_BASED RT_BIT_64(32)
166#define USE_IMMEDIATE16_SX8 RT_BIT_64(33)
167#define USE_IMMEDIATE32_SX8 RT_BIT_64(34)
168
169#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE64_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
170
171#define DIS_IS_EFFECTIVE_ADDR(flags) !!((flags) & (USE_BASE|USE_INDEX|USE_DISPLACEMENT32|USE_DISPLACEMENT64|USE_DISPLACEMENT16|USE_DISPLACEMENT8|USE_RIPDISPLACEMENT32))
172/** @} */
173
174/** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}
175 * @{
176 */
177#define USE_REG_RAX 0
178#define USE_REG_RCX 1
179#define USE_REG_RDX 2
180#define USE_REG_RBX 3
181#define USE_REG_RSP 4
182#define USE_REG_RBP 5
183#define USE_REG_RSI 6
184#define USE_REG_RDI 7
185#define USE_REG_R8 8
186#define USE_REG_R9 9
187#define USE_REG_R10 10
188#define USE_REG_R11 11
189#define USE_REG_R12 12
190#define USE_REG_R13 13
191#define USE_REG_R14 14
192#define USE_REG_R15 15
193/** @} */
194
195/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D"}
196 * @{
197 */
198#define USE_REG_EAX 0
199#define USE_REG_ECX 1
200#define USE_REG_EDX 2
201#define USE_REG_EBX 3
202#define USE_REG_ESP 4
203#define USE_REG_EBP 5
204#define USE_REG_ESI 6
205#define USE_REG_EDI 7
206#define USE_REG_R8D 8
207#define USE_REG_R9D 9
208#define USE_REG_R10D 10
209#define USE_REG_R11D 11
210#define USE_REG_R12D 12
211#define USE_REG_R13D 13
212#define USE_REG_R14D 14
213#define USE_REG_R15D 15
214
215/** @} */
216/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W"}
217 * @{
218 */
219#define USE_REG_AX 0
220#define USE_REG_CX 1
221#define USE_REG_DX 2
222#define USE_REG_BX 3
223#define USE_REG_SP 4
224#define USE_REG_BP 5
225#define USE_REG_SI 6
226#define USE_REG_DI 7
227#define USE_REG_R8W 8
228#define USE_REG_R9W 9
229#define USE_REG_R10W 10
230#define USE_REG_R11W 11
231#define USE_REG_R12W 12
232#define USE_REG_R13W 13
233#define USE_REG_R14W 14
234#define USE_REG_R15W 15
235/** @} */
236
237/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "SPL", "BPL", "SIL", "DIL"}
238 * @{
239 */
240#define USE_REG_AL 0
241#define USE_REG_CL 1
242#define USE_REG_DL 2
243#define USE_REG_BL 3
244#define USE_REG_AH 4
245#define USE_REG_CH 5
246#define USE_REG_DH 6
247#define USE_REG_BH 7
248#define USE_REG_R8B 8
249#define USE_REG_R9B 9
250#define USE_REG_R10B 10
251#define USE_REG_R11B 11
252#define USE_REG_R12B 12
253#define USE_REG_R13B 13
254#define USE_REG_R14B 14
255#define USE_REG_R15B 15
256#define USE_REG_SPL 16
257#define USE_REG_BPL 17
258#define USE_REG_SIL 18
259#define USE_REG_DIL 19
260
261/** @} */
262
263/** index in {ES, CS, SS, DS, FS, GS}
264 * @{
265 */
266typedef enum
267{
268 DIS_SELREG_ES = 0,
269 DIS_SELREG_CS = 1,
270 DIS_SELREG_SS = 2,
271 DIS_SELREG_DS = 3,
272 DIS_SELREG_FS = 4,
273 DIS_SELREG_GS = 5,
274 /** The usual 32-bit paranoia. */
275 DIS_SEGREG_32BIT_HACK = 0x7fffffff
276} DIS_SELREG;
277/** @} */
278
279#define USE_REG_FP0 0
280#define USE_REG_FP1 1
281#define USE_REG_FP2 2
282#define USE_REG_FP3 3
283#define USE_REG_FP4 4
284#define USE_REG_FP5 5
285#define USE_REG_FP6 6
286#define USE_REG_FP7 7
287
288#define USE_REG_CR0 0
289#define USE_REG_CR1 1
290#define USE_REG_CR2 2
291#define USE_REG_CR3 3
292#define USE_REG_CR4 4
293#define USE_REG_CR8 8
294
295#define USE_REG_DR0 0
296#define USE_REG_DR1 1
297#define USE_REG_DR2 2
298#define USE_REG_DR3 3
299#define USE_REG_DR4 4
300#define USE_REG_DR5 5
301#define USE_REG_DR6 6
302#define USE_REG_DR7 7
303
304#define USE_REG_MMX0 0
305#define USE_REG_MMX1 1
306#define USE_REG_MMX2 2
307#define USE_REG_MMX3 3
308#define USE_REG_MMX4 4
309#define USE_REG_MMX5 5
310#define USE_REG_MMX6 6
311#define USE_REG_MMX7 7
312
313#define USE_REG_XMM0 0
314#define USE_REG_XMM1 1
315#define USE_REG_XMM2 2
316#define USE_REG_XMM3 3
317#define USE_REG_XMM4 4
318#define USE_REG_XMM5 5
319#define USE_REG_XMM6 6
320#define USE_REG_XMM7 7
321
322/** Used by DISQueryParamVal & EMIQueryParamVal
323 * @{
324 */
325#define PARAM_VAL8 RT_BIT(0)
326#define PARAM_VAL16 RT_BIT(1)
327#define PARAM_VAL32 RT_BIT(2)
328#define PARAM_VAL64 RT_BIT(3)
329#define PARAM_VALFARPTR16 RT_BIT(4)
330#define PARAM_VALFARPTR32 RT_BIT(5)
331
332#define PARMTYPE_REGISTER 1
333#define PARMTYPE_ADDRESS 2
334#define PARMTYPE_IMMEDIATE 3
335
336typedef struct
337{
338 uint32_t type;
339 uint32_t size;
340 uint64_t flags;
341
342 union
343 {
344 uint8_t val8;
345 uint16_t val16;
346 uint32_t val32;
347 uint64_t val64;
348
349 struct
350 {
351 uint16_t sel;
352 uint32_t offset;
353 } farptr;
354 } val;
355
356} OP_PARAMVAL;
357/** Pointer to opcode parameter value. */
358typedef OP_PARAMVAL *POP_PARAMVAL;
359
360typedef enum
361{
362 PARAM_DEST,
363 PARAM_SOURCE
364} PARAM_TYPE;
365
366/** @} */
367
368/**
369 * Operand Parameter.
370 */
371typedef struct _OP_PARAMETER
372{
373 /** @todo switch param and parval and move disp64 and flags up here with the other 64-bit vars to get more natural alignment and save space. */
374 int param;
375 uint64_t parval;
376#ifndef DIS_SEPARATE_FORMATTER
377 char szParam[32];
378#endif
379
380 int32_t disp8, disp16, disp32;
381 uint32_t size;
382
383 int64_t disp64;
384 uint64_t flags;
385
386 union
387 {
388 uint32_t reg_gen;
389 /** ST(0) - ST(7) */
390 uint32_t reg_fp;
391 /** MMX0 - MMX7 */
392 uint32_t reg_mmx;
393 /** XMM0 - XMM7 */
394 uint32_t reg_xmm;
395 /** {ES, CS, SS, DS, FS, GS} */
396 DIS_SELREG reg_seg;
397 /** TR0-TR7 (?) */
398 uint32_t reg_test;
399 /** CR0-CR4 */
400 uint32_t reg_ctrl;
401 /** DR0-DR7 */
402 uint32_t reg_dbg;
403 } base;
404 union
405 {
406 uint32_t reg_gen;
407 } index;
408
409 /** 2, 4 or 8. */
410 uint32_t scale;
411
412} OP_PARAMETER;
413/** Pointer to opcode parameter. */
414typedef OP_PARAMETER *POP_PARAMETER;
415/** Pointer to opcode parameter. */
416typedef const OP_PARAMETER *PCOP_PARAMETER;
417
418
419struct _OPCODE;
420/** Pointer to opcode. */
421typedef struct _OPCODE *POPCODE;
422/** Pointer to const opcode. */
423typedef const struct _OPCODE *PCOPCODE;
424
425typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, unsigned size, void *pvUserdata);
426typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
427
428/* forward decl */
429struct _DISCPUSTATE;
430/** Pointer to the disassembler CPU state. */
431typedef struct _DISCPUSTATE *PDISCPUSTATE;
432
433/** Parser callback.
434 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
435typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
436typedef FNDISPARSE *PFNDISPARSE;
437
438typedef struct _DISCPUSTATE
439{
440 /* Global setting */
441 DISCPUMODE mode;
442
443 /* Per instruction prefix settings */
444 uint32_t prefix;
445 /** segment prefix value. */
446 DIS_SELREG enmPrefixSeg;
447 /** rex prefix value (64 bits only */
448 uint32_t prefix_rex;
449 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
450 DISCPUMODE addrmode;
451 /** operand mode (16 or 32 bits). (CPUMODE_*) */
452 DISCPUMODE opmode;
453
454 OP_PARAMETER param1;
455 OP_PARAMETER param2;
456 OP_PARAMETER param3;
457
458 /** ModRM fields. */
459 union
460 {
461 /* Bitfield view */
462 struct
463 {
464 unsigned Rm : 4;
465 unsigned Reg : 4;
466 unsigned Mod : 2;
467 } Bits;
468 /* unsigned view */
469 unsigned u;
470 } ModRM;
471
472 /** SIB fields. */
473 union
474 {
475 /* Bitfield view */
476 struct
477 {
478 unsigned Base : 4;
479 unsigned Index : 4;
480 unsigned Scale : 2;
481 } Bits;
482 /* unsigned view */
483 unsigned u;
484 } SIB;
485
486 int32_t disp;
487
488 /** First opcode byte of instruction. */
489 uint8_t opcode;
490 /** Last prefix byte (for SSE2 extension tables) */
491 uint8_t lastprefix;
492 RTUINTPTR opaddr;
493 uint32_t opsize;
494#ifndef DIS_CORE_ONLY
495 /** Opcode format string for current instruction. */
496 const char *pszOpcode;
497#endif
498
499 /** Internal: pointer to disassembly function table */
500 PFNDISPARSE *pfnDisasmFnTable;
501 /** Internal: instruction filter */
502 uint32_t uFilter;
503
504 /** Pointer to the current instruction. */
505 PCOPCODE pCurInstr;
506
507 void *apvUserData[3];
508
509 /** Optional read function */
510 PFN_DIS_READBYTES pfnReadBytes;
511#ifdef __L4ENV__
512 jmp_buf *pJumpBuffer;
513#endif /* __L4ENV__ */
514} DISCPUSTATE;
515
516/** Pointer to a const disassembler CPU state. */
517typedef DISCPUSTATE const *PCDISCPUSTATE;
518
519/** Opcode. */
520#pragma pack(4)
521typedef struct _OPCODE
522{
523#ifndef DIS_CORE_ONLY
524 const char *pszOpcode;
525#endif
526 uint8_t idxParse1;
527 uint8_t idxParse2;
528 uint8_t idxParse3;
529 uint16_t opcode;
530 uint16_t param1;
531 uint16_t param2;
532 uint16_t param3;
533
534 unsigned optype;
535} OPCODE;
536#pragma pack()
537
538
539/**
540 * Disassembles a code block.
541 *
542 * @returns VBox error code
543 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
544 * set correctly.
545 * @param pvCodeBlock Pointer to the strunction to disassemble.
546 * @param cbMax Maximum number of bytes to disassemble.
547 * @param pcbSize Where to store the size of the instruction.
548 * NULL is allowed.
549 *
550 *
551 * @todo Define output callback.
552 * @todo Using signed integers as sizes is a bit odd. There are still
553 * some GCC warnings about mixing signed and unsigend integers.
554 * @todo Need to extend this interface to include a code address so we
555 * can dissassemble GC code. Perhaps a new function is better...
556 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
557 * This means *pcbSize >= cbMax sometimes.
558 */
559DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
560
561/**
562 * Disassembles one instruction
563 *
564 * @returns VBox error code
565 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
566 * set correctly.
567 * @param pu8Instruction Pointer to the instrunction to disassemble.
568 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
569 * @param pcbSize Where to store the size of the instruction.
570 * NULL is allowed.
571 * @param pszOutput Storage for disassembled instruction
572 *
573 * @todo Define output callback.
574 */
575DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
576
577/**
578 * Disassembles one instruction
579 *
580 * @returns VBox error code
581 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
582 * set correctly.
583 * @param pu8Instruction Pointer to the strunction to disassemble.
584 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
585 * @param pcbSize Where to store the size of the instruction.
586 * NULL is allowed.
587 * @param pszOutput Storage for disassembled instruction
588 * @param uFilter Instruction type filter
589 *
590 * @todo Define output callback.
591 */
592DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
593 char *pszOutput, unsigned uFilter);
594
595/**
596 * Parses one instruction.
597 * The result is found in pCpu.
598 *
599 * @returns VBox error code
600 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
601 * @param InstructionAddr Pointer to the instruction to parse.
602 * @param pcbInstruction Where to store the size of the instruction.
603 * NULL is allowed.
604 */
605DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
606
607/**
608 * Parses one guest instruction.
609 * The result is found in pCpu and pcbInstruction.
610 *
611 * @returns VBox status code.
612 * @param InstructionAddr Address of the instruction to decode. What this means
613 * is left to the pfnReadBytes function.
614 * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
615 * @param pfnReadBytes Callback for reading instruction bytes.
616 * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
617 * @param pCpu Pointer to cpu structure. Will be initialized.
618 * @param pcbInstruction Where to store the size of the instruction.
619 * NULL is allowed.
620 */
621DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
622 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
623
624DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
625DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
626DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
627
628/**
629 * Returns the value of the parameter in pParam
630 *
631 * @returns VBox error code
632 * @param pCtx Exception structure pointer
633 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
634 * set correctly.
635 * @param pParam Pointer to the parameter to parse
636 * @param pParamVal Pointer to parameter value (OUT)
637 * @param parmtype Parameter type
638 *
639 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
640 *
641 */
642DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
643DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize);
644
645DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
646DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
647DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
648DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
649DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal);
650DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
651DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
652DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
653DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
654DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
655DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val);
656DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
657DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
658DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
659DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
660
661
662/**
663 * Try resolve an address into a symbol name.
664 *
665 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
666 *
667 * @returns VBox status code.
668 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
669 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
670 * content of pszBuf is truncated and zero terminated.
671 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
672 *
673 * @param pCpu Pointer to the disassembler CPU state.
674 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
675 * DIS_FMT_SEL_GET_REG to access this.
676 * @param uAddress The segment address.
677 * @param pszBuf Where to store the symbol name
678 * @param cchBuf The size of the buffer.
679 * @param poff If not a perfect match, then this is where the offset from the return
680 * symbol to the specified address is returned.
681 * @param pvUser The user argument.
682 */
683typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
684/** Pointer to a FNDISGETSYMBOL(). */
685typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
686
687/**
688 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
689 */
690#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
691
692/**
693 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
694 * @returns Selector value.
695 */
696#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
697
698/**
699 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
700 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
701 */
702#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
703
704/** @internal */
705#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
706/** @internal */
707#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
708
709
710/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
711 * @{
712 */
713/** Put the address to the right. */
714#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
715/** Put the address to the left. */
716#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
717/** Put the address in comments.
718 * For some assemblers this implies placing it to the right. */
719#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
720/** Put the instruction bytes to the right of the disassembly. */
721#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
722/** Put the instruction bytes to the left of the disassembly. */
723#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
724/** Put the instruction bytes in comments.
725 * For some assemblers this implies placing the bytes to the right. */
726#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
727/** Put the bytes in square brackets. */
728#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
729/** Put spaces between the bytes. */
730#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
731/** Display the relative +/- offset of branch instructions that uses relative addresses,
732 * and put the target address in parenthesis. */
733#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
734/** Strict assembly. The assembly should, when ever possible, make the
735 * assembler reproduce the exact same binary. (Refers to the yasm
736 * strict keyword.) */
737#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
738/** Checks if the given flags are a valid combination. */
739#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
740 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
741 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
742 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
743 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
744 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
745 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
746 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
747 )
748/** @} */
749
750DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
751DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
752DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
753DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
754DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
755DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
756
757/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
758
759
760__END_DECLS
761
762#endif
763
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette