VirtualBox

source: vbox/trunk/include/VBox/dis.h@ 10016

Last change on this file since 10016 was 10016, checked in by vboxsync, 16 years ago

Corrected parameter types (const).
Use SELMToFlatEx instead of SELMValidateAndConvertCSAddr when disassembling instructions.
(the latter is too strict)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 29.0 KB
Line 
1/** @file
2 * DIS - The VirtualBox Disassembler.
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_disasm_h
31#define ___VBox_disasm_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/disopcode.h>
36
37#if defined(__L4ENV__)
38#include <setjmp.h>
39#endif
40
41__BEGIN_DECLS
42
43
44/** CPU mode flags (DISCPUSTATE::mode).
45 * @{
46 */
47typedef enum
48{
49 CPUMODE_16BIT = 1,
50 CPUMODE_32BIT = 2,
51 CPUMODE_64BIT = 3,
52 /** hack forcing the size of the enum to 32-bits. */
53 CPUMODE_MAKE_32BIT_HACK = 0x7fffffff
54} DISCPUMODE;
55/** @} */
56
57/** Prefix byte flags
58 * @{
59 */
60#define PREFIX_NONE 0
61/** non-default address size. */
62#define PREFIX_ADDRSIZE RT_BIT(0)
63/** non-default operand size. */
64#define PREFIX_OPSIZE RT_BIT(1)
65/** lock prefix. */
66#define PREFIX_LOCK RT_BIT(2)
67/** segment prefix. */
68#define PREFIX_SEG RT_BIT(3)
69/** rep(e) prefix (not a prefix, but we'll treat is as one). */
70#define PREFIX_REP RT_BIT(4)
71/** rep(e) prefix (not a prefix, but we'll treat is as one). */
72#define PREFIX_REPNE RT_BIT(5)
73/** REX prefix (64 bits) */
74#define PREFIX_REX RT_BIT(6)
75/** @} */
76
77/** 64 bits prefix byte flags
78 * @{
79 */
80#define PREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
81#define PREFIX_REX_FLAGS PREFIX_REX_OP_2_FLAGS(OP_PARM_REX)
82#define PREFIX_REX_FLAGS_B PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
83#define PREFIX_REX_FLAGS_X PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
84#define PREFIX_REX_FLAGS_XB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
85#define PREFIX_REX_FLAGS_R PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
86#define PREFIX_REX_FLAGS_RB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
87#define PREFIX_REX_FLAGS_RX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
88#define PREFIX_REX_FLAGS_RXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
89#define PREFIX_REX_FLAGS_W PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
90#define PREFIX_REX_FLAGS_WB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
91#define PREFIX_REX_FLAGS_WX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
92#define PREFIX_REX_FLAGS_WXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
93#define PREFIX_REX_FLAGS_WR PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
94#define PREFIX_REX_FLAGS_WRB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
95#define PREFIX_REX_FLAGS_WRX PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
96#define PREFIX_REX_FLAGS_WRXB PREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
97/** @} */
98
99/**
100 * Operand type.
101 */
102#define OPTYPE_INVALID RT_BIT(0)
103#define OPTYPE_HARMLESS RT_BIT(1)
104#define OPTYPE_CONTROLFLOW RT_BIT(2)
105#define OPTYPE_POTENTIALLY_DANGEROUS RT_BIT(3)
106#define OPTYPE_DANGEROUS RT_BIT(4)
107#define OPTYPE_PORTIO RT_BIT(5)
108#define OPTYPE_PRIVILEGED RT_BIT(6)
109#define OPTYPE_PRIVILEGED_NOTRAP RT_BIT(7)
110#define OPTYPE_UNCOND_CONTROLFLOW RT_BIT(8)
111#define OPTYPE_RELATIVE_CONTROLFLOW RT_BIT(9)
112#define OPTYPE_COND_CONTROLFLOW RT_BIT(10)
113#define OPTYPE_INTERRUPT RT_BIT(11)
114#define OPTYPE_ILLEGAL RT_BIT(12)
115#define OPTYPE_RRM_DANGEROUS RT_BIT(14) /**< Some additional dangerouse ones when recompiling raw r0. */
116#define OPTYPE_RRM_DANGEROUS_16 RT_BIT(15) /**< Some additional dangerouse ones when recompiling 16-bit raw r0. */
117#define OPTYPE_RRM_MASK (OPTYPE_RRM_DANGEROUS | OPTYPE_RRM_DANGEROUS_16)
118#define OPTYPE_INHIBIT_IRQS RT_BIT(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
119#define OPTYPE_PORTIO_READ RT_BIT(17)
120#define OPTYPE_PORTIO_WRITE RT_BIT(18)
121#define OPTYPE_INVALID_64 RT_BIT(19) /**< Invalid in 64 bits mode */
122#define OPTYPE_ONLY_64 RT_BIT(20) /**< Only valid in 64 bits mode */
123#define OPTYPE_DEFAULT_64_OP_SIZE RT_BIT(21) /**< Default 64 bits operand size */
124#define OPTYPE_FORCED_64_OP_SIZE RT_BIT(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
125#define OPTYPE_REXB_EXTENDS_OPREG RT_BIT(23) /**< REX.B extends the register field in the opcode byte */
126#define OPTYPE_ALL (0xffffffff)
127
128/** Parameter usage flags.
129 * @{
130 */
131#define USE_BASE RT_BIT_64(0)
132#define USE_INDEX RT_BIT_64(1)
133#define USE_SCALE RT_BIT_64(2)
134#define USE_REG_GEN8 RT_BIT_64(3)
135#define USE_REG_GEN16 RT_BIT_64(4)
136#define USE_REG_GEN32 RT_BIT_64(5)
137#define USE_REG_GEN64 RT_BIT_64(6)
138#define USE_REG_FP RT_BIT_64(7)
139#define USE_REG_MMX RT_BIT_64(8)
140#define USE_REG_XMM RT_BIT_64(9)
141#define USE_REG_CR RT_BIT_64(10)
142#define USE_REG_DBG RT_BIT_64(11)
143#define USE_REG_SEG RT_BIT_64(12)
144#define USE_REG_TEST RT_BIT_64(13)
145#define USE_DISPLACEMENT8 RT_BIT_64(14)
146#define USE_DISPLACEMENT16 RT_BIT_64(15)
147#define USE_DISPLACEMENT32 RT_BIT_64(16)
148#define USE_DISPLACEMENT64 RT_BIT_64(17)
149#define USE_RIPDISPLACEMENT32 RT_BIT_64(18)
150#define USE_IMMEDIATE8 RT_BIT_64(19)
151#define USE_IMMEDIATE8_REL RT_BIT_64(20)
152#define USE_IMMEDIATE16 RT_BIT_64(21)
153#define USE_IMMEDIATE16_REL RT_BIT_64(22)
154#define USE_IMMEDIATE32 RT_BIT_64(23)
155#define USE_IMMEDIATE32_REL RT_BIT_64(24)
156#define USE_IMMEDIATE64 RT_BIT_64(25)
157#define USE_IMMEDIATE64_REL RT_BIT_64(26)
158#define USE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
159#define USE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
160#define USE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
161#define USE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
162/** DS:ESI */
163#define USE_POINTER_DS_BASED RT_BIT_64(31)
164/** ES:EDI */
165#define USE_POINTER_ES_BASED RT_BIT_64(32)
166#define USE_IMMEDIATE16_SX8 RT_BIT_64(33)
167#define USE_IMMEDIATE32_SX8 RT_BIT_64(34)
168
169#define USE_IMMEDIATE (USE_IMMEDIATE8|USE_IMMEDIATE16|USE_IMMEDIATE32|USE_IMMEDIATE64|USE_IMMEDIATE8_REL|USE_IMMEDIATE16_REL|USE_IMMEDIATE32_REL|USE_IMMEDIATE64_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE_ADDR_16_32|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE_ADDR_16_16|USE_IMMEDIATE16_SX8|USE_IMMEDIATE32_SX8)
170
171#define DIS_IS_EFFECTIVE_ADDR(flags) !!((flags) & (USE_BASE|USE_INDEX|USE_DISPLACEMENT32|USE_DISPLACEMENT64|USE_DISPLACEMENT16|USE_DISPLACEMENT8|USE_RIPDISPLACEMENT32))
172/** @} */
173
174/** index in {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"}
175 * @{
176 */
177#define USE_REG_RAX 0
178#define USE_REG_RCX 1
179#define USE_REG_RDX 2
180#define USE_REG_RBX 3
181#define USE_REG_RSP 4
182#define USE_REG_RBP 5
183#define USE_REG_RSI 6
184#define USE_REG_RDI 7
185#define USE_REG_R8 8
186#define USE_REG_R9 9
187#define USE_REG_R10 10
188#define USE_REG_R11 11
189#define USE_REG_R12 12
190#define USE_REG_R13 13
191#define USE_REG_R14 14
192#define USE_REG_R15 15
193/** @} */
194
195/** index in {"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D"}
196 * @{
197 */
198#define USE_REG_EAX 0
199#define USE_REG_ECX 1
200#define USE_REG_EDX 2
201#define USE_REG_EBX 3
202#define USE_REG_ESP 4
203#define USE_REG_EBP 5
204#define USE_REG_ESI 6
205#define USE_REG_EDI 7
206#define USE_REG_R8D 8
207#define USE_REG_R9D 9
208#define USE_REG_R10D 10
209#define USE_REG_R11D 11
210#define USE_REG_R12D 12
211#define USE_REG_R13D 13
212#define USE_REG_R14D 14
213#define USE_REG_R15D 15
214
215/** @} */
216/** index in {"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W"}
217 * @{
218 */
219#define USE_REG_AX 0
220#define USE_REG_CX 1
221#define USE_REG_DX 2
222#define USE_REG_BX 3
223#define USE_REG_SP 4
224#define USE_REG_BP 5
225#define USE_REG_SI 6
226#define USE_REG_DI 7
227#define USE_REG_R8W 8
228#define USE_REG_R9W 9
229#define USE_REG_R10W 10
230#define USE_REG_R11W 11
231#define USE_REG_R12W 12
232#define USE_REG_R13W 13
233#define USE_REG_R14W 14
234#define USE_REG_R15W 15
235/** @} */
236
237/** index in {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "SPL", "BPL", "SIL", "DIL"}
238 * @{
239 */
240#define USE_REG_AL 0
241#define USE_REG_CL 1
242#define USE_REG_DL 2
243#define USE_REG_BL 3
244#define USE_REG_AH 4
245#define USE_REG_CH 5
246#define USE_REG_DH 6
247#define USE_REG_BH 7
248#define USE_REG_R8B 8
249#define USE_REG_R9B 9
250#define USE_REG_R10B 10
251#define USE_REG_R11B 11
252#define USE_REG_R12B 12
253#define USE_REG_R13B 13
254#define USE_REG_R14B 14
255#define USE_REG_R15B 15
256#define USE_REG_SPL 16
257#define USE_REG_BPL 17
258#define USE_REG_SIL 18
259#define USE_REG_DIL 19
260
261/** @} */
262
263/** index in {ES, CS, SS, DS, FS, GS}
264 * @{
265 */
266typedef enum
267{
268 DIS_SELREG_ES = 0,
269 DIS_SELREG_CS = 1,
270 DIS_SELREG_SS = 2,
271 DIS_SELREG_DS = 3,
272 DIS_SELREG_FS = 4,
273 DIS_SELREG_GS = 5,
274 /** The usual 32-bit paranoia. */
275 DIS_SEGREG_32BIT_HACK = 0x7fffffff
276} DIS_SELREG;
277/** @} */
278
279#define USE_REG_FP0 0
280#define USE_REG_FP1 1
281#define USE_REG_FP2 2
282#define USE_REG_FP3 3
283#define USE_REG_FP4 4
284#define USE_REG_FP5 5
285#define USE_REG_FP6 6
286#define USE_REG_FP7 7
287
288#define USE_REG_CR0 0
289#define USE_REG_CR1 1
290#define USE_REG_CR2 2
291#define USE_REG_CR3 3
292#define USE_REG_CR4 4
293
294#define USE_REG_DR0 0
295#define USE_REG_DR1 1
296#define USE_REG_DR2 2
297#define USE_REG_DR3 3
298#define USE_REG_DR4 4
299#define USE_REG_DR5 5
300#define USE_REG_DR6 6
301#define USE_REG_DR7 7
302
303#define USE_REG_MMX0 0
304#define USE_REG_MMX1 1
305#define USE_REG_MMX2 2
306#define USE_REG_MMX3 3
307#define USE_REG_MMX4 4
308#define USE_REG_MMX5 5
309#define USE_REG_MMX6 6
310#define USE_REG_MMX7 7
311
312#define USE_REG_XMM0 0
313#define USE_REG_XMM1 1
314#define USE_REG_XMM2 2
315#define USE_REG_XMM3 3
316#define USE_REG_XMM4 4
317#define USE_REG_XMM5 5
318#define USE_REG_XMM6 6
319#define USE_REG_XMM7 7
320
321/** Used by DISQueryParamVal & EMIQueryParamVal
322 * @{
323 */
324#define PARAM_VAL8 RT_BIT(0)
325#define PARAM_VAL16 RT_BIT(1)
326#define PARAM_VAL32 RT_BIT(2)
327#define PARAM_VAL64 RT_BIT(3)
328#define PARAM_VALFARPTR16 RT_BIT(4)
329#define PARAM_VALFARPTR32 RT_BIT(5)
330
331#define PARMTYPE_REGISTER 1
332#define PARMTYPE_ADDRESS 2
333#define PARMTYPE_IMMEDIATE 3
334
335typedef struct
336{
337 uint32_t type;
338 uint32_t size;
339 uint64_t flags;
340
341 union
342 {
343 uint8_t val8;
344 uint16_t val16;
345 uint32_t val32;
346 uint64_t val64;
347
348 struct
349 {
350 uint16_t sel;
351 uint32_t offset;
352 } farptr;
353 } val;
354
355} OP_PARAMVAL;
356/** Pointer to opcode parameter value. */
357typedef OP_PARAMVAL *POP_PARAMVAL;
358
359typedef enum
360{
361 PARAM_DEST,
362 PARAM_SOURCE
363} PARAM_TYPE;
364
365/** @} */
366
367/**
368 * Operand Parameter.
369 */
370typedef struct _OP_PARAMETER
371{
372 /** @todo switch param and parval and move disp64 and flags up here with the other 64-bit vars to get more natural alignment and save space. */
373 int param;
374 uint64_t parval;
375#ifndef DIS_SEPARATE_FORMATTER
376 char szParam[32];
377#endif
378
379 int32_t disp8, disp16, disp32;
380 uint32_t size;
381
382 int64_t disp64;
383 uint64_t flags;
384
385 union
386 {
387 uint32_t reg_gen;
388 /** ST(0) - ST(7) */
389 uint32_t reg_fp;
390 /** MMX0 - MMX7 */
391 uint32_t reg_mmx;
392 /** XMM0 - XMM7 */
393 uint32_t reg_xmm;
394 /** {ES, CS, SS, DS, FS, GS} */
395 DIS_SELREG reg_seg;
396 /** TR0-TR7 (?) */
397 uint32_t reg_test;
398 /** CR0-CR4 */
399 uint32_t reg_ctrl;
400 /** DR0-DR7 */
401 uint32_t reg_dbg;
402 } base;
403 union
404 {
405 uint32_t reg_gen;
406 } index;
407
408 /** 2, 4 or 8. */
409 uint32_t scale;
410
411} OP_PARAMETER;
412/** Pointer to opcode parameter. */
413typedef OP_PARAMETER *POP_PARAMETER;
414/** Pointer to opcode parameter. */
415typedef const OP_PARAMETER *PCOP_PARAMETER;
416
417
418struct _OPCODE;
419/** Pointer to opcode. */
420typedef struct _OPCODE *POPCODE;
421/** Pointer to const opcode. */
422typedef const struct _OPCODE *PCOPCODE;
423
424typedef DECLCALLBACK(int) FN_DIS_READBYTES(RTUINTPTR pSrc, uint8_t *pDest, unsigned size, void *pvUserdata);
425typedef FN_DIS_READBYTES *PFN_DIS_READBYTES;
426
427/* forward decl */
428struct _DISCPUSTATE;
429/** Pointer to the disassembler CPU state. */
430typedef struct _DISCPUSTATE *PDISCPUSTATE;
431
432/** Parser callback.
433 * @remark no DECLCALLBACK() here because it's considered to be internal (really, I'm too lazy to update all the functions). */
434typedef unsigned FNDISPARSE(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
435typedef FNDISPARSE *PFNDISPARSE;
436
437typedef struct _DISCPUSTATE
438{
439 /* Global setting */
440 DISCPUMODE mode;
441
442 /* Per instruction prefix settings */
443 uint32_t prefix;
444 /** segment prefix value. */
445 DIS_SELREG enmPrefixSeg;
446 /** rex prefix value (64 bits only */
447 uint32_t prefix_rex;
448 /** addressing mode (16 or 32 bits). (CPUMODE_*) */
449 DISCPUMODE addrmode;
450 /** operand mode (16 or 32 bits). (CPUMODE_*) */
451 DISCPUMODE opmode;
452
453 OP_PARAMETER param1;
454 OP_PARAMETER param2;
455 OP_PARAMETER param3;
456
457 /** ModRM fields. */
458 union
459 {
460 /* Bitfield view */
461 struct
462 {
463 unsigned Rm : 4;
464 unsigned Reg : 4;
465 unsigned Mod : 2;
466 } Bits;
467 /* unsigned view */
468 unsigned u;
469 } ModRM;
470
471 /** SIB fields. */
472 union
473 {
474 /* Bitfield view */
475 struct
476 {
477 unsigned Base : 4;
478 unsigned Index : 4;
479 unsigned Scale : 2;
480 } Bits;
481 /* unsigned view */
482 unsigned u;
483 } SIB;
484
485 int32_t disp;
486
487 /** First opcode byte of instruction. */
488 uint8_t opcode;
489 /** Last prefix byte (for SSE2 extension tables) */
490 uint8_t lastprefix;
491 RTUINTPTR opaddr;
492 uint32_t opsize;
493#ifndef DIS_CORE_ONLY
494 /** Opcode format string for current instruction. */
495 const char *pszOpcode;
496#endif
497
498 /** Internal: pointer to disassembly function table */
499 PFNDISPARSE *pfnDisasmFnTable;
500 /** Internal: instruction filter */
501 uint32_t uFilter;
502
503 /** Pointer to the current instruction. */
504 PCOPCODE pCurInstr;
505
506 void *apvUserData[3];
507
508 /** Optional read function */
509 PFN_DIS_READBYTES pfnReadBytes;
510#ifdef __L4ENV__
511 jmp_buf *pJumpBuffer;
512#endif /* __L4ENV__ */
513} DISCPUSTATE;
514
515/** Pointer to a const disassembler CPU state. */
516typedef DISCPUSTATE const *PCDISCPUSTATE;
517
518/** Opcode. */
519#pragma pack(4)
520typedef struct _OPCODE
521{
522#ifndef DIS_CORE_ONLY
523 const char *pszOpcode;
524#endif
525 uint8_t idxParse1;
526 uint8_t idxParse2;
527 uint8_t idxParse3;
528 uint16_t opcode;
529 uint16_t param1;
530 uint16_t param2;
531 uint16_t param3;
532
533 unsigned optype;
534} OPCODE;
535#pragma pack()
536
537
538/**
539 * Disassembles a code block.
540 *
541 * @returns VBox error code
542 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
543 * set correctly.
544 * @param pvCodeBlock Pointer to the strunction to disassemble.
545 * @param cbMax Maximum number of bytes to disassemble.
546 * @param pcbSize Where to store the size of the instruction.
547 * NULL is allowed.
548 *
549 *
550 * @todo Define output callback.
551 * @todo Using signed integers as sizes is a bit odd. There are still
552 * some GCC warnings about mixing signed and unsigend integers.
553 * @todo Need to extend this interface to include a code address so we
554 * can dissassemble GC code. Perhaps a new function is better...
555 * @remark cbMax isn't respected as a boundry. DISInstr() will read beyond cbMax.
556 * This means *pcbSize >= cbMax sometimes.
557 */
558DISDECL(int) DISBlock(PDISCPUSTATE pCpu, RTUINTPTR pvCodeBlock, unsigned cbMax, unsigned *pSize);
559
560/**
561 * Disassembles one instruction
562 *
563 * @returns VBox error code
564 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
565 * set correctly.
566 * @param pu8Instruction Pointer to the instrunction to disassemble.
567 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
568 * @param pcbSize Where to store the size of the instruction.
569 * NULL is allowed.
570 * @param pszOutput Storage for disassembled instruction
571 *
572 * @todo Define output callback.
573 */
574DISDECL(int) DISInstr(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, unsigned u32EipOffset, unsigned *pcbSize, char *pszOutput);
575
576/**
577 * Disassembles one instruction
578 *
579 * @returns VBox error code
580 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
581 * set correctly.
582 * @param pu8Instruction Pointer to the strunction to disassemble.
583 * @param u32EipOffset Offset to add to instruction address to get the real virtual address
584 * @param pcbSize Where to store the size of the instruction.
585 * NULL is allowed.
586 * @param pszOutput Storage for disassembled instruction
587 * @param uFilter Instruction type filter
588 *
589 * @todo Define output callback.
590 */
591DISDECL(int) DISInstrEx(PDISCPUSTATE pCpu, RTUINTPTR pu8Instruction, uint32_t u32EipOffset, uint32_t *pcbSize,
592 char *pszOutput, unsigned uFilter);
593
594/**
595 * Parses one instruction.
596 * The result is found in pCpu.
597 *
598 * @returns VBox error code
599 * @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
600 * @param InstructionAddr Pointer to the instruction to parse.
601 * @param pcbInstruction Where to store the size of the instruction.
602 * NULL is allowed.
603 */
604DISDECL(int) DISCoreOne(PDISCPUSTATE pCpu, RTUINTPTR InstructionAddr, unsigned *pcbInstruction);
605
606/**
607 * Parses one guest instruction.
608 * The result is found in pCpu and pcbInstruction.
609 *
610 * @returns VBox status code.
611 * @param InstructionAddr Address of the instruction to decode. What this means
612 * is left to the pfnReadBytes function.
613 * @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
614 * @param pfnReadBytes Callback for reading instruction bytes.
615 * @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
616 * @param pCpu Pointer to cpu structure. Will be initialized.
617 * @param pcbInstruction Where to store the size of the instruction.
618 * NULL is allowed.
619 */
620DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
621 PDISCPUSTATE pCpu, unsigned *pcbInstruction);
622
623DISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
624DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam);
625DISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu);
626
627/**
628 * Returns the value of the parameter in pParam
629 *
630 * @returns VBox error code
631 * @param pCtx Exception structure pointer
632 * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
633 * set correctly.
634 * @param pParam Pointer to the parameter to parse
635 * @param pParamVal Pointer to parameter value (OUT)
636 * @param parmtype Parameter type
637 *
638 * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
639 *
640 */
641DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype);
642DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize);
643
644DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
645DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
646DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
647DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
648DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal);
649DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, PCPUMSELREGHID *ppSelHidReg);
650DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
651DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
652DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
653DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
654DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val);
655DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
656DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
657DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
658DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
659
660
661/**
662 * Try resolve an address into a symbol name.
663 *
664 * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
665 *
666 * @returns VBox status code.
667 * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
668 * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
669 * content of pszBuf is truncated and zero terminated.
670 * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
671 *
672 * @param pCpu Pointer to the disassembler CPU state.
673 * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
674 * DIS_FMT_SEL_GET_REG to access this.
675 * @param uAddress The segment address.
676 * @param pszBuf Where to store the symbol name
677 * @param cchBuf The size of the buffer.
678 * @param poff If not a perfect match, then this is where the offset from the return
679 * symbol to the specified address is returned.
680 * @param pvUser The user argument.
681 */
682typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
683/** Pointer to a FNDISGETSYMBOL(). */
684typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
685
686/**
687 * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
688 */
689#define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
690
691/**
692 * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
693 * @returns Selector value.
694 */
695#define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
696
697/**
698 * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
699 * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
700 */
701#define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
702
703/** @internal */
704#define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
705/** @internal */
706#define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
707
708
709/** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
710 * @{
711 */
712/** Put the address to the right. */
713#define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
714/** Put the address to the left. */
715#define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
716/** Put the address in comments.
717 * For some assemblers this implies placing it to the right. */
718#define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
719/** Put the instruction bytes to the right of the disassembly. */
720#define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
721/** Put the instruction bytes to the left of the disassembly. */
722#define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
723/** Put the instruction bytes in comments.
724 * For some assemblers this implies placing the bytes to the right. */
725#define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
726/** Put the bytes in square brackets. */
727#define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
728/** Put spaces between the bytes. */
729#define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
730/** Display the relative +/- offset of branch instructions that uses relative addresses,
731 * and put the target address in parenthesis. */
732#define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
733/** Strict assembly. The assembly should, when ever possible, make the
734 * assembler reproduce the exact same binary. (Refers to the yasm
735 * strict keyword.) */
736#define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
737/** Checks if the given flags are a valid combination. */
738#define DIS_FMT_FLAGS_IS_VALID(fFlags) \
739 ( !((fFlags) & ~UINT32_C(0x000003ff)) \
740 && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
741 && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
742 || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
743 && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
744 && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
745 || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
746 )
747/** @} */
748
749DISDECL(size_t) DISFormatYasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
750DISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
751DISDECL(size_t) DISFormatMasm( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
752DISDECL(size_t) DISFormatMasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
753DISDECL(size_t) DISFormatGas( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf);
754DISDECL(size_t) DISFormatGasEx( PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
755
756/** @todo DISAnnotate(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, register reader, memory reader); */
757
758
759__END_DECLS
760
761#endif
762
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette