[1] | 1 | /** @file
|
---|
| 2 | * DIS - The VirtualBox Disassembler.
|
---|
| 3 | */
|
---|
| 4 |
|
---|
| 5 | /*
|
---|
[41658] | 6 | * Copyright (C) 2006-2012 Oracle Corporation
|
---|
[1] | 7 | *
|
---|
| 8 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
---|
| 9 | * available from http://www.virtualbox.org. This file is free software;
|
---|
| 10 | * you can redistribute it and/or modify it under the terms of the GNU
|
---|
[5999] | 11 | * General Public License (GPL) as published by the Free Software
|
---|
| 12 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
---|
| 13 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
---|
| 14 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
---|
| 15 | *
|
---|
| 16 | * The contents of this file may alternatively be used under the terms
|
---|
| 17 | * of the Common Development and Distribution License Version 1.0
|
---|
| 18 | * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
|
---|
| 19 | * VirtualBox OSE distribution, in which case the provisions of the
|
---|
| 20 | * CDDL are applicable instead of those of the GPL.
|
---|
| 21 | *
|
---|
| 22 | * You may elect to license modified versions of this file under the
|
---|
| 23 | * terms and conditions of either the GPL or the CDDL or both.
|
---|
[1] | 24 | */
|
---|
| 25 |
|
---|
[41675] | 26 | #ifndef ___VBox_dis_h
|
---|
| 27 | #define ___VBox_dis_h
|
---|
[1] | 28 |
|
---|
| 29 | #include <VBox/types.h>
|
---|
[1829] | 30 | #include <VBox/disopcode.h>
|
---|
[41692] | 31 | #include <iprt/assert.h>
|
---|
[1] | 32 |
|
---|
| 33 |
|
---|
[20374] | 34 | RT_C_DECLS_BEGIN
|
---|
[1] | 35 |
|
---|
| 36 |
|
---|
[41790] | 37 | /** @name Prefix byte flags (DISSTATE::fPrefix).
|
---|
[1] | 38 | * @{
|
---|
| 39 | */
|
---|
[41675] | 40 | #define DISPREFIX_NONE UINT8_C(0x00)
|
---|
[1] | 41 | /** non-default address size. */
|
---|
[41675] | 42 | #define DISPREFIX_ADDRSIZE UINT8_C(0x01)
|
---|
[1] | 43 | /** non-default operand size. */
|
---|
[41675] | 44 | #define DISPREFIX_OPSIZE UINT8_C(0x02)
|
---|
[1] | 45 | /** lock prefix. */
|
---|
[41675] | 46 | #define DISPREFIX_LOCK UINT8_C(0x04)
|
---|
[1] | 47 | /** segment prefix. */
|
---|
[41675] | 48 | #define DISPREFIX_SEG UINT8_C(0x08)
|
---|
[1] | 49 | /** rep(e) prefix (not a prefix, but we'll treat is as one). */
|
---|
[41675] | 50 | #define DISPREFIX_REP UINT8_C(0x10)
|
---|
[1] | 51 | /** rep(e) prefix (not a prefix, but we'll treat is as one). */
|
---|
[41675] | 52 | #define DISPREFIX_REPNE UINT8_C(0x20)
|
---|
[7000] | 53 | /** REX prefix (64 bits) */
|
---|
[41675] | 54 | #define DISPREFIX_REX UINT8_C(0x40)
|
---|
[1] | 55 | /** @} */
|
---|
| 56 |
|
---|
[41790] | 57 | /** @name 64 bits prefix byte flags (DISSTATE::fRexPrefix).
|
---|
[41676] | 58 | * Requires VBox/disopcode.h.
|
---|
[7000] | 59 | * @{
|
---|
| 60 | */
|
---|
[41676] | 61 | #define DISPREFIX_REX_OP_2_FLAGS(a) (a - OP_PARM_REX_START)
|
---|
[46993] | 62 | /*#define DISPREFIX_REX_FLAGS DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX) - 0, which is no flag */
|
---|
[41676] | 63 | #define DISPREFIX_REX_FLAGS_B DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_B)
|
---|
| 64 | #define DISPREFIX_REX_FLAGS_X DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_X)
|
---|
| 65 | #define DISPREFIX_REX_FLAGS_XB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_XB)
|
---|
| 66 | #define DISPREFIX_REX_FLAGS_R DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_R)
|
---|
| 67 | #define DISPREFIX_REX_FLAGS_RB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RB)
|
---|
| 68 | #define DISPREFIX_REX_FLAGS_RX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RX)
|
---|
| 69 | #define DISPREFIX_REX_FLAGS_RXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_RXB)
|
---|
| 70 | #define DISPREFIX_REX_FLAGS_W DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_W)
|
---|
| 71 | #define DISPREFIX_REX_FLAGS_WB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WB)
|
---|
| 72 | #define DISPREFIX_REX_FLAGS_WX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WX)
|
---|
| 73 | #define DISPREFIX_REX_FLAGS_WXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WXB)
|
---|
| 74 | #define DISPREFIX_REX_FLAGS_WR DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WR)
|
---|
| 75 | #define DISPREFIX_REX_FLAGS_WRB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRB)
|
---|
| 76 | #define DISPREFIX_REX_FLAGS_WRX DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRX)
|
---|
| 77 | #define DISPREFIX_REX_FLAGS_WRXB DISPREFIX_REX_OP_2_FLAGS(OP_PARM_REX_WRXB)
|
---|
[7000] | 78 | /** @} */
|
---|
[46993] | 79 | AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_B));
|
---|
| 80 | AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_X));
|
---|
| 81 | AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_W));
|
---|
| 82 | AssertCompile(RT_IS_POWER_OF_TWO(DISPREFIX_REX_FLAGS_R));
|
---|
[7000] | 83 |
|
---|
[41738] | 84 | /** @name Operand type (DISOPCODE::fOpType).
|
---|
[41674] | 85 | * @{
|
---|
[1] | 86 | */
|
---|
[41676] | 87 | #define DISOPTYPE_INVALID RT_BIT_32(0)
|
---|
| 88 | #define DISOPTYPE_HARMLESS RT_BIT_32(1)
|
---|
| 89 | #define DISOPTYPE_CONTROLFLOW RT_BIT_32(2)
|
---|
| 90 | #define DISOPTYPE_POTENTIALLY_DANGEROUS RT_BIT_32(3)
|
---|
| 91 | #define DISOPTYPE_DANGEROUS RT_BIT_32(4)
|
---|
| 92 | #define DISOPTYPE_PORTIO RT_BIT_32(5)
|
---|
| 93 | #define DISOPTYPE_PRIVILEGED RT_BIT_32(6)
|
---|
| 94 | #define DISOPTYPE_PRIVILEGED_NOTRAP RT_BIT_32(7)
|
---|
| 95 | #define DISOPTYPE_UNCOND_CONTROLFLOW RT_BIT_32(8)
|
---|
| 96 | #define DISOPTYPE_RELATIVE_CONTROLFLOW RT_BIT_32(9)
|
---|
| 97 | #define DISOPTYPE_COND_CONTROLFLOW RT_BIT_32(10)
|
---|
| 98 | #define DISOPTYPE_INTERRUPT RT_BIT_32(11)
|
---|
| 99 | #define DISOPTYPE_ILLEGAL RT_BIT_32(12)
|
---|
| 100 | #define DISOPTYPE_RRM_DANGEROUS RT_BIT_32(14) /**< Some additional dangerous ones when recompiling raw r0. */
|
---|
| 101 | #define DISOPTYPE_RRM_DANGEROUS_16 RT_BIT_32(15) /**< Some additional dangerous ones when recompiling 16-bit raw r0. */
|
---|
| 102 | #define DISOPTYPE_RRM_MASK (DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_RRM_DANGEROUS_16)
|
---|
| 103 | #define DISOPTYPE_INHIBIT_IRQS RT_BIT_32(16) /**< Will or can inhibit irqs (sti, pop ss, mov ss) */
|
---|
| 104 | #define DISOPTYPE_PORTIO_READ RT_BIT_32(17)
|
---|
| 105 | #define DISOPTYPE_PORTIO_WRITE RT_BIT_32(18)
|
---|
| 106 | #define DISOPTYPE_INVALID_64 RT_BIT_32(19) /**< Invalid in 64 bits mode */
|
---|
| 107 | #define DISOPTYPE_ONLY_64 RT_BIT_32(20) /**< Only valid in 64 bits mode */
|
---|
| 108 | #define DISOPTYPE_DEFAULT_64_OP_SIZE RT_BIT_32(21) /**< Default 64 bits operand size */
|
---|
| 109 | #define DISOPTYPE_FORCED_64_OP_SIZE RT_BIT_32(22) /**< Forced 64 bits operand size; regardless of prefix bytes */
|
---|
| 110 | #define DISOPTYPE_REXB_EXTENDS_OPREG RT_BIT_32(23) /**< REX.B extends the register field in the opcode byte */
|
---|
| 111 | #define DISOPTYPE_MOD_FIXED_11 RT_BIT_32(24) /**< modrm.mod is always 11b */
|
---|
| 112 | #define DISOPTYPE_FORCED_32_OP_SIZE_X86 RT_BIT_32(25) /**< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */
|
---|
[47412] | 113 | #define DISOPTYPE_SSE RT_BIT_32(29) /**< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! */
|
---|
| 114 | #define DISOPTYPE_MMX RT_BIT_32(30) /**< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! */
|
---|
| 115 | #define DISOPTYPE_FPU RT_BIT_32(31) /**< FPU instruction. Not implemented yet! */
|
---|
[41676] | 116 | #define DISOPTYPE_ALL UINT32_C(0xffffffff)
|
---|
[41674] | 117 | /** @} */
|
---|
[1] | 118 |
|
---|
[41674] | 119 | /** @name Parameter usage flags.
|
---|
[1] | 120 | * @{
|
---|
| 121 | */
|
---|
[41676] | 122 | #define DISUSE_BASE RT_BIT_64(0)
|
---|
| 123 | #define DISUSE_INDEX RT_BIT_64(1)
|
---|
| 124 | #define DISUSE_SCALE RT_BIT_64(2)
|
---|
| 125 | #define DISUSE_REG_GEN8 RT_BIT_64(3)
|
---|
| 126 | #define DISUSE_REG_GEN16 RT_BIT_64(4)
|
---|
| 127 | #define DISUSE_REG_GEN32 RT_BIT_64(5)
|
---|
| 128 | #define DISUSE_REG_GEN64 RT_BIT_64(6)
|
---|
| 129 | #define DISUSE_REG_FP RT_BIT_64(7)
|
---|
| 130 | #define DISUSE_REG_MMX RT_BIT_64(8)
|
---|
| 131 | #define DISUSE_REG_XMM RT_BIT_64(9)
|
---|
| 132 | #define DISUSE_REG_CR RT_BIT_64(10)
|
---|
| 133 | #define DISUSE_REG_DBG RT_BIT_64(11)
|
---|
| 134 | #define DISUSE_REG_SEG RT_BIT_64(12)
|
---|
| 135 | #define DISUSE_REG_TEST RT_BIT_64(13)
|
---|
| 136 | #define DISUSE_DISPLACEMENT8 RT_BIT_64(14)
|
---|
| 137 | #define DISUSE_DISPLACEMENT16 RT_BIT_64(15)
|
---|
| 138 | #define DISUSE_DISPLACEMENT32 RT_BIT_64(16)
|
---|
| 139 | #define DISUSE_DISPLACEMENT64 RT_BIT_64(17)
|
---|
| 140 | #define DISUSE_RIPDISPLACEMENT32 RT_BIT_64(18)
|
---|
| 141 | #define DISUSE_IMMEDIATE8 RT_BIT_64(19)
|
---|
| 142 | #define DISUSE_IMMEDIATE8_REL RT_BIT_64(20)
|
---|
| 143 | #define DISUSE_IMMEDIATE16 RT_BIT_64(21)
|
---|
| 144 | #define DISUSE_IMMEDIATE16_REL RT_BIT_64(22)
|
---|
| 145 | #define DISUSE_IMMEDIATE32 RT_BIT_64(23)
|
---|
| 146 | #define DISUSE_IMMEDIATE32_REL RT_BIT_64(24)
|
---|
| 147 | #define DISUSE_IMMEDIATE64 RT_BIT_64(25)
|
---|
| 148 | #define DISUSE_IMMEDIATE64_REL RT_BIT_64(26)
|
---|
| 149 | #define DISUSE_IMMEDIATE_ADDR_0_32 RT_BIT_64(27)
|
---|
| 150 | #define DISUSE_IMMEDIATE_ADDR_16_32 RT_BIT_64(28)
|
---|
| 151 | #define DISUSE_IMMEDIATE_ADDR_0_16 RT_BIT_64(29)
|
---|
| 152 | #define DISUSE_IMMEDIATE_ADDR_16_16 RT_BIT_64(30)
|
---|
[1] | 153 | /** DS:ESI */
|
---|
[41676] | 154 | #define DISUSE_POINTER_DS_BASED RT_BIT_64(31)
|
---|
[1] | 155 | /** ES:EDI */
|
---|
[41676] | 156 | #define DISUSE_POINTER_ES_BASED RT_BIT_64(32)
|
---|
| 157 | #define DISUSE_IMMEDIATE16_SX8 RT_BIT_64(33)
|
---|
| 158 | #define DISUSE_IMMEDIATE32_SX8 RT_BIT_64(34)
|
---|
| 159 | #define DISUSE_IMMEDIATE64_SX8 RT_BIT_64(36)
|
---|
[1] | 160 |
|
---|
[41676] | 161 | /** Mask of immediate use flags. */
|
---|
| 162 | #define DISUSE_IMMEDIATE ( DISUSE_IMMEDIATE8 \
|
---|
| 163 | | DISUSE_IMMEDIATE16 \
|
---|
| 164 | | DISUSE_IMMEDIATE32 \
|
---|
| 165 | | DISUSE_IMMEDIATE64 \
|
---|
| 166 | | DISUSE_IMMEDIATE8_REL \
|
---|
| 167 | | DISUSE_IMMEDIATE16_REL \
|
---|
| 168 | | DISUSE_IMMEDIATE32_REL \
|
---|
| 169 | | DISUSE_IMMEDIATE64_REL \
|
---|
| 170 | | DISUSE_IMMEDIATE_ADDR_0_32 \
|
---|
| 171 | | DISUSE_IMMEDIATE_ADDR_16_32 \
|
---|
| 172 | | DISUSE_IMMEDIATE_ADDR_0_16 \
|
---|
| 173 | | DISUSE_IMMEDIATE_ADDR_16_16 \
|
---|
| 174 | | DISUSE_IMMEDIATE16_SX8 \
|
---|
| 175 | | DISUSE_IMMEDIATE32_SX8 \
|
---|
| 176 | | DISUSE_IMMEDIATE64_SX8)
|
---|
| 177 | /** Check if the use flags indicates an effective address. */
|
---|
| 178 | #define DISUSE_IS_EFFECTIVE_ADDR(a_fUseFlags) (!!( (a_fUseFlags) \
|
---|
| 179 | & ( DISUSE_BASE \
|
---|
| 180 | | DISUSE_INDEX \
|
---|
| 181 | | DISUSE_DISPLACEMENT32 \
|
---|
| 182 | | DISUSE_DISPLACEMENT64 \
|
---|
| 183 | | DISUSE_DISPLACEMENT16 \
|
---|
| 184 | | DISUSE_DISPLACEMENT8 \
|
---|
| 185 | | DISUSE_RIPDISPLACEMENT32) ))
|
---|
[1] | 186 | /** @} */
|
---|
| 187 |
|
---|
[41727] | 188 | /** @name 64-bit general register indexes.
|
---|
| 189 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 190 | * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
|
---|
[41727] | 191 | * @note Safe to assume same values as the 16-bit and 32-bit general registers.
|
---|
[8142] | 192 | * @{
|
---|
| 193 | */
|
---|
[41727] | 194 | #define DISGREG_RAX UINT8_C(0)
|
---|
| 195 | #define DISGREG_RCX UINT8_C(1)
|
---|
| 196 | #define DISGREG_RDX UINT8_C(2)
|
---|
| 197 | #define DISGREG_RBX UINT8_C(3)
|
---|
| 198 | #define DISGREG_RSP UINT8_C(4)
|
---|
| 199 | #define DISGREG_RBP UINT8_C(5)
|
---|
| 200 | #define DISGREG_RSI UINT8_C(6)
|
---|
| 201 | #define DISGREG_RDI UINT8_C(7)
|
---|
| 202 | #define DISGREG_R8 UINT8_C(8)
|
---|
| 203 | #define DISGREG_R9 UINT8_C(9)
|
---|
| 204 | #define DISGREG_R10 UINT8_C(10)
|
---|
| 205 | #define DISGREG_R11 UINT8_C(11)
|
---|
| 206 | #define DISGREG_R12 UINT8_C(12)
|
---|
| 207 | #define DISGREG_R13 UINT8_C(13)
|
---|
| 208 | #define DISGREG_R14 UINT8_C(14)
|
---|
| 209 | #define DISGREG_R15 UINT8_C(15)
|
---|
[8142] | 210 | /** @} */
|
---|
| 211 |
|
---|
[41727] | 212 | /** @name 32-bit general register indexes.
|
---|
| 213 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 214 | * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
|
---|
[41727] | 215 | * @note Safe to assume same values as the 16-bit and 64-bit general registers.
|
---|
[1] | 216 | * @{
|
---|
| 217 | */
|
---|
[41727] | 218 | #define DISGREG_EAX UINT8_C(0)
|
---|
| 219 | #define DISGREG_ECX UINT8_C(1)
|
---|
| 220 | #define DISGREG_EDX UINT8_C(2)
|
---|
| 221 | #define DISGREG_EBX UINT8_C(3)
|
---|
| 222 | #define DISGREG_ESP UINT8_C(4)
|
---|
| 223 | #define DISGREG_EBP UINT8_C(5)
|
---|
| 224 | #define DISGREG_ESI UINT8_C(6)
|
---|
| 225 | #define DISGREG_EDI UINT8_C(7)
|
---|
| 226 | #define DISGREG_R8D UINT8_C(8)
|
---|
| 227 | #define DISGREG_R9D UINT8_C(9)
|
---|
| 228 | #define DISGREG_R10D UINT8_C(10)
|
---|
| 229 | #define DISGREG_R11D UINT8_C(11)
|
---|
| 230 | #define DISGREG_R12D UINT8_C(12)
|
---|
| 231 | #define DISGREG_R13D UINT8_C(13)
|
---|
| 232 | #define DISGREG_R14D UINT8_C(14)
|
---|
| 233 | #define DISGREG_R15D UINT8_C(15)
|
---|
[41676] | 234 | /** @} */
|
---|
[9919] | 235 |
|
---|
[41727] | 236 | /** @name 16-bit general register indexes.
|
---|
| 237 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 238 | * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
|
---|
[41727] | 239 | * @note Safe to assume same values as the 32-bit and 64-bit general registers.
|
---|
[1] | 240 | * @{
|
---|
| 241 | */
|
---|
[41727] | 242 | #define DISGREG_AX UINT8_C(0)
|
---|
| 243 | #define DISGREG_CX UINT8_C(1)
|
---|
| 244 | #define DISGREG_DX UINT8_C(2)
|
---|
| 245 | #define DISGREG_BX UINT8_C(3)
|
---|
| 246 | #define DISGREG_SP UINT8_C(4)
|
---|
| 247 | #define DISGREG_BP UINT8_C(5)
|
---|
| 248 | #define DISGREG_SI UINT8_C(6)
|
---|
| 249 | #define DISGREG_DI UINT8_C(7)
|
---|
| 250 | #define DISGREG_R8W UINT8_C(8)
|
---|
| 251 | #define DISGREG_R9W UINT8_C(9)
|
---|
| 252 | #define DISGREG_R10W UINT8_C(10)
|
---|
| 253 | #define DISGREG_R11W UINT8_C(11)
|
---|
| 254 | #define DISGREG_R12W UINT8_C(12)
|
---|
| 255 | #define DISGREG_R13W UINT8_C(13)
|
---|
| 256 | #define DISGREG_R14W UINT8_C(14)
|
---|
| 257 | #define DISGREG_R15W UINT8_C(15)
|
---|
[1] | 258 | /** @} */
|
---|
| 259 |
|
---|
[41727] | 260 | /** @name 8-bit general register indexes.
|
---|
| 261 | * This mostly (?) matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 262 | * DISOPPARAM::Base.idxGenReg and DISOPPARAM::Index.idxGenReg.
|
---|
[1] | 263 | * @{
|
---|
| 264 | */
|
---|
[41727] | 265 | #define DISGREG_AL UINT8_C(0)
|
---|
| 266 | #define DISGREG_CL UINT8_C(1)
|
---|
| 267 | #define DISGREG_DL UINT8_C(2)
|
---|
| 268 | #define DISGREG_BL UINT8_C(3)
|
---|
| 269 | #define DISGREG_AH UINT8_C(4)
|
---|
| 270 | #define DISGREG_CH UINT8_C(5)
|
---|
| 271 | #define DISGREG_DH UINT8_C(6)
|
---|
| 272 | #define DISGREG_BH UINT8_C(7)
|
---|
| 273 | #define DISGREG_R8B UINT8_C(8)
|
---|
| 274 | #define DISGREG_R9B UINT8_C(9)
|
---|
| 275 | #define DISGREG_R10B UINT8_C(10)
|
---|
| 276 | #define DISGREG_R11B UINT8_C(11)
|
---|
| 277 | #define DISGREG_R12B UINT8_C(12)
|
---|
| 278 | #define DISGREG_R13B UINT8_C(13)
|
---|
| 279 | #define DISGREG_R14B UINT8_C(14)
|
---|
| 280 | #define DISGREG_R15B UINT8_C(15)
|
---|
| 281 | #define DISGREG_SPL UINT8_C(16)
|
---|
| 282 | #define DISGREG_BPL UINT8_C(17)
|
---|
| 283 | #define DISGREG_SIL UINT8_C(18)
|
---|
| 284 | #define DISGREG_DIL UINT8_C(19)
|
---|
[1] | 285 | /** @} */
|
---|
| 286 |
|
---|
[41727] | 287 | /** @name Segment registerindexes.
|
---|
| 288 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 289 | * DISOPPARAM::Base.idxSegReg.
|
---|
[1] | 290 | * @{
|
---|
| 291 | */
|
---|
[9675] | 292 | typedef enum
|
---|
| 293 | {
|
---|
[41727] | 294 | DISSELREG_ES = 0,
|
---|
| 295 | DISSELREG_CS = 1,
|
---|
| 296 | DISSELREG_SS = 2,
|
---|
| 297 | DISSELREG_DS = 3,
|
---|
| 298 | DISSELREG_FS = 4,
|
---|
| 299 | DISSELREG_GS = 5,
|
---|
[41747] | 300 | /** End of the valid register index values. */
|
---|
| 301 | DISSELREG_END,
|
---|
[9675] | 302 | /** The usual 32-bit paranoia. */
|
---|
| 303 | DIS_SEGREG_32BIT_HACK = 0x7fffffff
|
---|
[41727] | 304 | } DISSELREG;
|
---|
[1] | 305 | /** @} */
|
---|
| 306 |
|
---|
[41728] | 307 | /** @name FPU register indexes.
|
---|
| 308 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 309 | * DISOPPARAM::Base.idxFpuReg.
|
---|
[41728] | 310 | * @{
|
---|
| 311 | */
|
---|
| 312 | #define DISFPREG_ST0 UINT8_C(0)
|
---|
| 313 | #define DISFPREG_ST1 UINT8_C(1)
|
---|
| 314 | #define DISFPREG_ST2 UINT8_C(2)
|
---|
| 315 | #define DISFPREG_ST3 UINT8_C(3)
|
---|
| 316 | #define DISFPREG_ST4 UINT8_C(4)
|
---|
| 317 | #define DISFPREG_ST5 UINT8_C(5)
|
---|
| 318 | #define DISFPREG_ST6 UINT8_C(6)
|
---|
| 319 | #define DISFPREG_ST7 UINT8_C(7)
|
---|
| 320 | /** @} */
|
---|
[1] | 321 |
|
---|
[41728] | 322 | /** @name Control register indexes.
|
---|
| 323 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 324 | * DISOPPARAM::Base.idxCtrlReg.
|
---|
[41728] | 325 | * @{
|
---|
| 326 | */
|
---|
| 327 | #define DISCREG_CR0 UINT8_C(0)
|
---|
| 328 | #define DISCREG_CR1 UINT8_C(1)
|
---|
| 329 | #define DISCREG_CR2 UINT8_C(2)
|
---|
| 330 | #define DISCREG_CR3 UINT8_C(3)
|
---|
| 331 | #define DISCREG_CR4 UINT8_C(4)
|
---|
| 332 | #define DISCREG_CR8 UINT8_C(8)
|
---|
| 333 | /** @} */
|
---|
[1] | 334 |
|
---|
[41728] | 335 | /** @name Debug register indexes.
|
---|
| 336 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 337 | * DISOPPARAM::Base.idxDbgReg.
|
---|
[41728] | 338 | * @{
|
---|
| 339 | */
|
---|
| 340 | #define DISDREG_DR0 UINT8_C(0)
|
---|
| 341 | #define DISDREG_DR1 UINT8_C(1)
|
---|
| 342 | #define DISDREG_DR2 UINT8_C(2)
|
---|
| 343 | #define DISDREG_DR3 UINT8_C(3)
|
---|
| 344 | #define DISDREG_DR4 UINT8_C(4)
|
---|
| 345 | #define DISDREG_DR5 UINT8_C(5)
|
---|
| 346 | #define DISDREG_DR6 UINT8_C(6)
|
---|
| 347 | #define DISDREG_DR7 UINT8_C(7)
|
---|
| 348 | /** @} */
|
---|
[1] | 349 |
|
---|
[41728] | 350 | /** @name MMX register indexes.
|
---|
| 351 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 352 | * DISOPPARAM::Base.idxMmxReg.
|
---|
[41728] | 353 | * @{
|
---|
| 354 | */
|
---|
| 355 | #define DISMREG_MMX0 UINT8_C(0)
|
---|
| 356 | #define DISMREG_MMX1 UINT8_C(1)
|
---|
| 357 | #define DISMREG_MMX2 UINT8_C(2)
|
---|
| 358 | #define DISMREG_MMX3 UINT8_C(3)
|
---|
| 359 | #define DISMREG_MMX4 UINT8_C(4)
|
---|
| 360 | #define DISMREG_MMX5 UINT8_C(5)
|
---|
| 361 | #define DISMREG_MMX6 UINT8_C(6)
|
---|
| 362 | #define DISMREG_MMX7 UINT8_C(7)
|
---|
| 363 | /** @} */
|
---|
[1] | 364 |
|
---|
[41728] | 365 | /** @name SSE register indexes.
|
---|
| 366 | * This matches the AMD64 register encoding. It is found used in
|
---|
[41744] | 367 | * DISOPPARAM::Base.idxXmmReg.
|
---|
[41728] | 368 | * @{
|
---|
| 369 | */
|
---|
| 370 | #define DISXREG_XMM0 UINT8_C(0)
|
---|
| 371 | #define DISXREG_XMM1 UINT8_C(1)
|
---|
| 372 | #define DISXREG_XMM2 UINT8_C(2)
|
---|
| 373 | #define DISXREG_XMM3 UINT8_C(3)
|
---|
| 374 | #define DISXREG_XMM4 UINT8_C(4)
|
---|
| 375 | #define DISXREG_XMM5 UINT8_C(5)
|
---|
| 376 | #define DISXREG_XMM6 UINT8_C(6)
|
---|
| 377 | #define DISXREG_XMM7 UINT8_C(7)
|
---|
[41744] | 378 | /** @} */
|
---|
[1] | 379 |
|
---|
| 380 |
|
---|
| 381 | /**
|
---|
[41745] | 382 | * Opcode parameter (operand) details.
|
---|
[1] | 383 | */
|
---|
[41692] | 384 | typedef struct DISOPPARAM
|
---|
[1] | 385 | {
|
---|
[41678] | 386 | /** A combination of DISUSE_XXX. */
|
---|
| 387 | uint64_t fUse;
|
---|
[41744] | 388 | /** Immediate value or address, applicable if any of the flags included in
|
---|
| 389 | * DISUSE_IMMEDIATE are set in fUse. */
|
---|
| 390 | uint64_t uValue;
|
---|
| 391 | /** Disposition. */
|
---|
[41662] | 392 | union
|
---|
| 393 | {
|
---|
[41744] | 394 | /** 64-bit displacement, applicable if DISUSE_DISPLACEMENT64 is set in fUse. */
|
---|
[41662] | 395 | int64_t i64;
|
---|
[41744] | 396 | uint64_t u64;
|
---|
| 397 | /** 32-bit displacement, applicable if DISUSE_DISPLACEMENT32 or
|
---|
| 398 | * DISUSE_RIPDISPLACEMENT32 is set in fUse. */
|
---|
[41662] | 399 | int32_t i32;
|
---|
[41744] | 400 | uint32_t u32;
|
---|
| 401 | /** 16-bit displacement, applicable if DISUSE_DISPLACEMENT16 is set in fUse. */
|
---|
[41662] | 402 | int32_t i16;
|
---|
[41744] | 403 | uint32_t u16;
|
---|
| 404 | /** 8-bit displacement, applicable if DISUSE_DISPLACEMENT8 is set in fUse. */
|
---|
[41662] | 405 | int32_t i8;
|
---|
| 406 | uint32_t u8;
|
---|
| 407 | } uDisp;
|
---|
[41744] | 408 | /** The base register from ModR/M or SIB, applicable if DISUSE_BASE is
|
---|
| 409 | * set in fUse. */
|
---|
[1] | 410 | union
|
---|
| 411 | {
|
---|
[41744] | 412 | /** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
|
---|
| 413 | * DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
|
---|
| 414 | uint8_t idxGenReg;
|
---|
| 415 | /** FPU stack register index (DISFPREG_XXX), applicable if DISUSE_REG_FP is
|
---|
| 416 | * set in fUse. 1:1 indexes. */
|
---|
| 417 | uint8_t idxFpuReg;
|
---|
| 418 | /** MMX register index (DISMREG_XXX), applicable if DISUSE_REG_MMX is
|
---|
| 419 | * set in fUse. 1:1 indexes. */
|
---|
| 420 | uint8_t idxMmxReg;
|
---|
| 421 | /** SSE register index (DISXREG_XXX), applicable if DISUSE_REG_XMM is
|
---|
| 422 | * set in fUse. 1:1 indexes. */
|
---|
| 423 | uint8_t idxXmmReg;
|
---|
| 424 | /** Segment register index (DISSELREG_XXX), applicable if DISUSE_REG_SEG is
|
---|
| 425 | * set in fUse. */
|
---|
| 426 | uint8_t idxSegReg;
|
---|
| 427 | /** Test register, TR0-TR7, present on early IA32 CPUs, applicable if
|
---|
| 428 | * DISUSE_REG_TEST is set in fUse. No index defines for these. */
|
---|
| 429 | uint8_t idxTestReg;
|
---|
| 430 | /** Control register index (DISCREG_XXX), applicable if DISUSE_REG_CR is
|
---|
| 431 | * set in fUse. 1:1 indexes. */
|
---|
| 432 | uint8_t idxCtrlReg;
|
---|
| 433 | /** Debug register index (DISDREG_XXX), applicable if DISUSE_REG_DBG is
|
---|
| 434 | * set in fUse. 1:1 indexes. */
|
---|
| 435 | uint8_t idxDbgReg;
|
---|
| 436 | } Base;
|
---|
[41743] | 437 | /** The SIB index register meaning, applicable if DISUSE_INDEX is
|
---|
| 438 | * set in fUse. */
|
---|
[1] | 439 | union
|
---|
| 440 | {
|
---|
[41743] | 441 | /** General register index (DISGREG_XXX), applicable if DISUSE_REG_GEN8,
|
---|
| 442 | * DISUSE_REG_GEN16, DISUSE_REG_GEN32 or DISUSE_REG_GEN64 is set in fUse. */
|
---|
| 443 | uint8_t idxGenReg;
|
---|
| 444 | } Index;
|
---|
[41742] | 445 | /** 2, 4 or 8, if DISUSE_SCALE is set in fUse. */
|
---|
| 446 | uint8_t uScale;
|
---|
[41663] | 447 | /** Parameter size. */
|
---|
| 448 | uint8_t cb;
|
---|
[41744] | 449 | /** Copy of the corresponding DISOPCODE::fParam1 / DISOPCODE::fParam2 /
|
---|
| 450 | * DISOPCODE::fParam3. */
|
---|
| 451 | uint32_t fParam;
|
---|
[41692] | 452 | } DISOPPARAM;
|
---|
| 453 | AssertCompileSize(DISOPPARAM, 32);
|
---|
[1] | 454 | /** Pointer to opcode parameter. */
|
---|
[41692] | 455 | typedef DISOPPARAM *PDISOPPARAM;
|
---|
[1] | 456 | /** Pointer to opcode parameter. */
|
---|
[41730] | 457 | typedef const DISOPPARAM *PCDISOPPARAM;
|
---|
[1] | 458 |
|
---|
| 459 |
|
---|
[41730] | 460 | /**
|
---|
| 461 | * Opcode descriptor.
|
---|
| 462 | */
|
---|
| 463 | typedef struct DISOPCODE
|
---|
| 464 | {
|
---|
| 465 | #ifndef DIS_CORE_ONLY
|
---|
| 466 | const char *pszOpcode;
|
---|
| 467 | #endif
|
---|
[41738] | 468 | /** Parameter \#1 parser index. */
|
---|
[41730] | 469 | uint8_t idxParse1;
|
---|
[41738] | 470 | /** Parameter \#2 parser index. */
|
---|
[41730] | 471 | uint8_t idxParse2;
|
---|
[41738] | 472 | /** Parameter \#3 parser index. */
|
---|
[41730] | 473 | uint8_t idxParse3;
|
---|
[41738] | 474 | /** Unused padding. */
|
---|
[41730] | 475 | uint8_t uUnused;
|
---|
[41737] | 476 | /** The opcode identifier. This DIS specific, @see grp_dis_opcodes and
|
---|
| 477 | * VBox/disopcode.h. */
|
---|
| 478 | uint16_t uOpcode;
|
---|
[41738] | 479 | /** Parameter \#1 info, @see grp_dis_opparam. */
|
---|
| 480 | uint16_t fParam1;
|
---|
| 481 | /** Parameter \#2 info, @see grp_dis_opparam. */
|
---|
| 482 | uint16_t fParam2;
|
---|
| 483 | /** Parameter \#3 info, @see grp_dis_opparam. */
|
---|
| 484 | uint16_t fParam3;
|
---|
| 485 | /** Operand type flags, DISOPTYPE_XXX. */
|
---|
| 486 | uint32_t fOpType;
|
---|
[41730] | 487 | } DISOPCODE;
|
---|
[1] | 488 | /** Pointer to const opcode. */
|
---|
[41690] | 489 | typedef const struct DISOPCODE *PCDISOPCODE;
|
---|
[1] | 490 |
|
---|
[41730] | 491 |
|
---|
[41658] | 492 | /**
|
---|
[41760] | 493 | * Callback for reading instruction bytes.
|
---|
[41658] | 494 | *
|
---|
[41790] | 495 | * @returns VBox status code, bytes in DISSTATE::abInstr and byte count in
|
---|
| 496 | * DISSTATE::cbCachedInstr.
|
---|
[41760] | 497 | * @param pDis Pointer to the disassembler state. The user
|
---|
[41790] | 498 | * argument can be found in DISSTATE::pvUser if needed.
|
---|
[41760] | 499 | * @param offInstr The offset relative to the start of the instruction.
|
---|
| 500 | *
|
---|
| 501 | * To get the source address, add this to
|
---|
[41790] | 502 | * DISSTATE::uInstrAddr.
|
---|
[41760] | 503 | *
|
---|
| 504 | * To calculate the destination buffer address, use it
|
---|
[41790] | 505 | * as an index into DISSTATE::abInstr.
|
---|
[41760] | 506 | *
|
---|
| 507 | * @param cbMinRead The minimum number of bytes to read.
|
---|
| 508 | * @param cbMaxRead The maximum number of bytes that may be read.
|
---|
[41658] | 509 | */
|
---|
[41790] | 510 | typedef DECLCALLBACK(int) FNDISREADBYTES(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead);
|
---|
[41658] | 511 | /** Pointer to a opcode byte reader. */
|
---|
| 512 | typedef FNDISREADBYTES *PFNDISREADBYTES;
|
---|
[1] | 513 |
|
---|
| 514 | /** Parser callback.
|
---|
[41786] | 515 | * @remark no DECLCALLBACK() here because it's considered to be internal and
|
---|
| 516 | * there is no point in enforcing CDECL. */
|
---|
[41793] | 517 | typedef size_t FNDISPARSE(size_t offInstr, PCDISOPCODE pOp, PDISSTATE pDis, PDISOPPARAM pParam);
|
---|
[41730] | 518 | /** Pointer to a disassembler parser function. */
|
---|
[1] | 519 | typedef FNDISPARSE *PFNDISPARSE;
|
---|
[41730] | 520 | /** Pointer to a const disassembler parser function pointer. */
|
---|
[41692] | 521 | typedef PFNDISPARSE const *PCPFNDISPARSE;
|
---|
[1] | 522 |
|
---|
[41730] | 523 | /**
|
---|
| 524 | * The diassembler state and result.
|
---|
| 525 | */
|
---|
[41790] | 526 | typedef struct DISSTATE
|
---|
[1] | 527 | {
|
---|
[41792] | 528 | /** The number of valid bytes in abInstr. */
|
---|
| 529 | uint8_t cbCachedInstr;
|
---|
| 530 | /** SIB fields. */
|
---|
[8333] | 531 | union
|
---|
| 532 | {
|
---|
[41658] | 533 | /** Bitfield view */
|
---|
[8333] | 534 | struct
|
---|
| 535 | {
|
---|
[41792] | 536 | uint8_t Base;
|
---|
| 537 | uint8_t Index;
|
---|
| 538 | uint8_t Scale;
|
---|
[8333] | 539 | } Bits;
|
---|
[41792] | 540 | } SIB;
|
---|
| 541 | /** ModRM fields. */
|
---|
[8333] | 542 | union
|
---|
| 543 | {
|
---|
[41658] | 544 | /** Bitfield view */
|
---|
[8333] | 545 | struct
|
---|
| 546 | {
|
---|
[41792] | 547 | uint8_t Rm;
|
---|
| 548 | uint8_t Reg;
|
---|
| 549 | uint8_t Mod;
|
---|
[8333] | 550 | } Bits;
|
---|
[41792] | 551 | } ModRM;
|
---|
[41692] | 552 | /** The CPU mode (DISCPUMODE). */
|
---|
[41736] | 553 | uint8_t uCpuMode;
|
---|
[41692] | 554 | /** The addressing mode (DISCPUMODE). */
|
---|
[41735] | 555 | uint8_t uAddrMode;
|
---|
[41692] | 556 | /** The operand mode (DISCPUMODE). */
|
---|
[41735] | 557 | uint8_t uOpMode;
|
---|
[41692] | 558 | /** Per instruction prefix settings. */
|
---|
[41734] | 559 | uint8_t fPrefix;
|
---|
[41692] | 560 | /** REX prefix value (64 bits only). */
|
---|
[41733] | 561 | uint8_t fRexPrefix;
|
---|
[41727] | 562 | /** Segment prefix value (DISSELREG). */
|
---|
[41692] | 563 | uint8_t idxSegPrefix;
|
---|
| 564 | /** Last prefix byte (for SSE2 extension tables). */
|
---|
[41733] | 565 | uint8_t bLastPrefix;
|
---|
[41798] | 566 | /** Last significan opcode byte of instruction. */
|
---|
[41733] | 567 | uint8_t bOpCode;
|
---|
[41692] | 568 | /** The size of the prefix bytes. */
|
---|
[41727] | 569 | uint8_t cbPrefix;
|
---|
[41692] | 570 | /** The instruction size. */
|
---|
[41732] | 571 | uint8_t cbInstr;
|
---|
[41792] | 572 | /** Unused bytes. */
|
---|
| 573 | uint8_t abUnused[3];
|
---|
[1] | 574 | /** Internal: instruction filter */
|
---|
[41674] | 575 | uint32_t fFilter;
|
---|
[41692] | 576 | /** Internal: pointer to disassembly function table */
|
---|
| 577 | PCPFNDISPARSE pfnDisasmFnTable;
|
---|
| 578 | #if ARCH_BITS == 32
|
---|
| 579 | uint32_t uPtrPadding1;
|
---|
| 580 | #endif
|
---|
[1] | 581 | /** Pointer to the current instruction. */
|
---|
[41690] | 582 | PCDISOPCODE pCurInstr;
|
---|
[41692] | 583 | #if ARCH_BITS == 32
|
---|
| 584 | uint32_t uPtrPadding2;
|
---|
[41658] | 585 | #endif
|
---|
[41792] | 586 | /** The instruction bytes. */
|
---|
| 587 | uint8_t abInstr[16];
|
---|
| 588 | /** SIB displacment. */
|
---|
| 589 | int32_t i32SibDisp;
|
---|
| 590 |
|
---|
| 591 | /** Return code set by a worker function like the opcode bytes readers. */
|
---|
| 592 | int32_t rc;
|
---|
[41692] | 593 | /** The address of the instruction. */
|
---|
| 594 | RTUINTPTR uInstrAddr;
|
---|
[41658] | 595 | /** Optional read function */
|
---|
| 596 | PFNDISREADBYTES pfnReadBytes;
|
---|
[41692] | 597 | #if ARCH_BITS == 32
|
---|
| 598 | uint32_t uPadding3;
|
---|
| 599 | #endif
|
---|
[41731] | 600 | /** User data supplied as an argument to the APIs. */
|
---|
| 601 | void *pvUser;
|
---|
[41692] | 602 | #if ARCH_BITS == 32
|
---|
[41731] | 603 | uint32_t uPadding4;
|
---|
[41692] | 604 | #endif
|
---|
[41792] | 605 | /** Parameters. */
|
---|
| 606 | DISOPPARAM Param1;
|
---|
| 607 | DISOPPARAM Param2;
|
---|
| 608 | DISOPPARAM Param3;
|
---|
[41790] | 609 | } DISSTATE;
|
---|
[41792] | 610 | AssertCompileSize(DISSTATE, 0xb8);
|
---|
[1] | 611 |
|
---|
[41790] | 612 | /** @deprecated Use DISSTATE and change Cpu and DisState to Dis. */
|
---|
| 613 | typedef DISSTATE DISCPUSTATE;
|
---|
[20530] | 614 |
|
---|
[1] | 615 |
|
---|
[41790] | 616 |
|
---|
[41669] | 617 | DISDECL(int) DISInstrToStr(void const *pvInstr, DISCPUMODE enmCpuMode,
|
---|
[41790] | 618 | PDISSTATE pDis, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
|
---|
[41671] | 619 | DISDECL(int) DISInstrToStrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
|
---|
[41790] | 620 | PDISSTATE pDis, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
|
---|
[41671] | 621 | DISDECL(int) DISInstrToStrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode,
|
---|
| 622 | PFNDISREADBYTES pfnReadBytes, void *pvUser, uint32_t uFilter,
|
---|
[41790] | 623 | PDISSTATE pDis, uint32_t *pcbInstr, char *pszOutput, size_t cbOutput);
|
---|
[1] | 624 |
|
---|
[41790] | 625 | DISDECL(int) DISInstr(void const *pvInstr, DISCPUMODE enmCpuMode, PDISSTATE pDis, uint32_t *pcbInstr);
|
---|
[41674] | 626 | DISDECL(int) DISInstrWithReader(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, PFNDISREADBYTES pfnReadBytes, void *pvUser,
|
---|
[41790] | 627 | PDISSTATE pDis, uint32_t *pcbInstr);
|
---|
[41886] | 628 | DISDECL(int) DISInstrEx(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t uFilter,
|
---|
| 629 | PFNDISREADBYTES pfnReadBytes, void *pvUser,
|
---|
| 630 | PDISSTATE pDis, uint32_t *pcbInstr);
|
---|
| 631 | DISDECL(int) DISInstrWithPrefetchedBytes(RTUINTPTR uInstrAddr, DISCPUMODE enmCpuMode, uint32_t fFilter,
|
---|
| 632 | void const *pvPrefetched, size_t cbPretched,
|
---|
| 633 | PFNDISREADBYTES pfnReadBytes, void *pvUser,
|
---|
| 634 | PDISSTATE pDis, uint32_t *pcbInstr);
|
---|
[1] | 635 |
|
---|
[41790] | 636 | DISDECL(int) DISGetParamSize(PCDISSTATE pDis, PCDISOPPARAM pParam);
|
---|
| 637 | DISDECL(DISSELREG) DISDetectSegReg(PCDISSTATE pDis, PCDISOPPARAM pParam);
|
---|
| 638 | DISDECL(uint8_t) DISQuerySegPrefixByte(PCDISSTATE pDis);
|
---|
[1] | 639 |
|
---|
[41731] | 640 |
|
---|
| 641 |
|
---|
| 642 | /** @name Flags returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
|
---|
| 643 | * @{
|
---|
| 644 | */
|
---|
| 645 | #define DISQPV_FLAG_8 UINT8_C(0x01)
|
---|
| 646 | #define DISQPV_FLAG_16 UINT8_C(0x02)
|
---|
| 647 | #define DISQPV_FLAG_32 UINT8_C(0x04)
|
---|
| 648 | #define DISQPV_FLAG_64 UINT8_C(0x08)
|
---|
| 649 | #define DISQPV_FLAG_FARPTR16 UINT8_C(0x10)
|
---|
| 650 | #define DISQPV_FLAG_FARPTR32 UINT8_C(0x20)
|
---|
| 651 | /** @} */
|
---|
| 652 |
|
---|
| 653 | /** @name Types returned by DISQueryParamVal (DISQPVPARAMVAL::flags).
|
---|
| 654 | * @{ */
|
---|
| 655 | #define DISQPV_TYPE_REGISTER UINT8_C(1)
|
---|
| 656 | #define DISQPV_TYPE_ADDRESS UINT8_C(2)
|
---|
| 657 | #define DISQPV_TYPE_IMMEDIATE UINT8_C(3)
|
---|
| 658 | /** @} */
|
---|
| 659 |
|
---|
| 660 | typedef struct
|
---|
| 661 | {
|
---|
| 662 | union
|
---|
| 663 | {
|
---|
| 664 | uint8_t val8;
|
---|
| 665 | uint16_t val16;
|
---|
| 666 | uint32_t val32;
|
---|
| 667 | uint64_t val64;
|
---|
| 668 |
|
---|
| 669 | struct
|
---|
| 670 | {
|
---|
| 671 | uint16_t sel;
|
---|
| 672 | uint32_t offset;
|
---|
| 673 | } farptr;
|
---|
| 674 | } val;
|
---|
| 675 |
|
---|
| 676 | uint8_t type;
|
---|
| 677 | uint8_t size;
|
---|
| 678 | uint8_t flags;
|
---|
| 679 | } DISQPVPARAMVAL;
|
---|
| 680 | /** Pointer to opcode parameter value. */
|
---|
| 681 | typedef DISQPVPARAMVAL *PDISQPVPARAMVAL;
|
---|
| 682 |
|
---|
| 683 | /** Indicates which parameter DISQueryParamVal should operate on. */
|
---|
| 684 | typedef enum DISQPVWHICH
|
---|
| 685 | {
|
---|
| 686 | DISQPVWHICH_DST = 1,
|
---|
| 687 | DISQPVWHICH_SRC,
|
---|
| 688 | DISQPVWHAT_32_BIT_HACK = 0x7fffffff
|
---|
| 689 | } DISQPVWHICH;
|
---|
[41790] | 690 | DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype);
|
---|
| 691 | DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PCDISSTATE pDis, PCDISOPPARAM pParam, void **ppReg, size_t *pcbSize);
|
---|
[41731] | 692 |
|
---|
[10016] | 693 | DISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal);
|
---|
| 694 | DISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal);
|
---|
| 695 | DISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal);
|
---|
| 696 | DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
|
---|
[41727] | 697 | DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
|
---|
[42186] | 698 | DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg);
|
---|
[8142] | 699 | DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
|
---|
| 700 | DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);
|
---|
| 701 | DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32);
|
---|
| 702 | DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64);
|
---|
[41727] | 703 | DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val);
|
---|
[8142] | 704 | DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg);
|
---|
| 705 | DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg);
|
---|
| 706 | DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg);
|
---|
| 707 | DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg);
|
---|
[1] | 708 |
|
---|
[9266] | 709 |
|
---|
| 710 | /**
|
---|
| 711 | * Try resolve an address into a symbol name.
|
---|
| 712 | *
|
---|
| 713 | * For use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
|
---|
| 714 | *
|
---|
| 715 | * @returns VBox status code.
|
---|
| 716 | * @retval VINF_SUCCESS on success, pszBuf contains the full symbol name.
|
---|
| 717 | * @retval VINF_BUFFER_OVERFLOW if pszBuf is too small the symbol name. The
|
---|
| 718 | * content of pszBuf is truncated and zero terminated.
|
---|
| 719 | * @retval VERR_SYMBOL_NOT_FOUND if no matching symbol was found for the address.
|
---|
| 720 | *
|
---|
[41790] | 721 | * @param pDis Pointer to the disassembler CPU state.
|
---|
[9266] | 722 | * @param u32Sel The selector value. Use DIS_FMT_SEL_IS_REG, DIS_FMT_SEL_GET_VALUE,
|
---|
| 723 | * DIS_FMT_SEL_GET_REG to access this.
|
---|
| 724 | * @param uAddress The segment address.
|
---|
| 725 | * @param pszBuf Where to store the symbol name
|
---|
| 726 | * @param cchBuf The size of the buffer.
|
---|
| 727 | * @param poff If not a perfect match, then this is where the offset from the return
|
---|
| 728 | * symbol to the specified address is returned.
|
---|
| 729 | * @param pvUser The user argument.
|
---|
| 730 | */
|
---|
[41790] | 731 | typedef DECLCALLBACK(int) FNDISGETSYMBOL(PCDISSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser);
|
---|
[9266] | 732 | /** Pointer to a FNDISGETSYMBOL(). */
|
---|
| 733 | typedef FNDISGETSYMBOL *PFNDISGETSYMBOL;
|
---|
| 734 |
|
---|
| 735 | /**
|
---|
| 736 | * Checks if the FNDISGETSYMBOL argument u32Sel is a register or not.
|
---|
| 737 | */
|
---|
| 738 | #define DIS_FMT_SEL_IS_REG(u32Sel) ( !!((u32Sel) & RT_BIT(31)) )
|
---|
| 739 |
|
---|
| 740 | /**
|
---|
| 741 | * Extracts the selector value from the FNDISGETSYMBOL argument u32Sel.
|
---|
| 742 | * @returns Selector value.
|
---|
| 743 | */
|
---|
| 744 | #define DIS_FMT_SEL_GET_VALUE(u32Sel) ( (RTSEL)(u32Sel) )
|
---|
| 745 |
|
---|
| 746 | /**
|
---|
| 747 | * Extracts the register number from the FNDISGETSYMBOL argument u32Sel.
|
---|
| 748 | * @returns USE_REG_CS, USE_REG_SS, USE_REG_DS, USE_REG_ES, USE_REG_FS or USE_REG_FS.
|
---|
| 749 | */
|
---|
| 750 | #define DIS_FMT_SEL_GET_REG(u32Sel) ( ((u32Sel) >> 16) & 0xf )
|
---|
| 751 |
|
---|
| 752 | /** @internal */
|
---|
| 753 | #define DIS_FMT_SEL_FROM_REG(uReg) ( ((uReg) << 16) | RT_BIT(31) | 0xffff )
|
---|
| 754 | /** @internal */
|
---|
| 755 | #define DIS_FMT_SEL_FROM_VALUE(Sel) ( (Sel) & 0xffff )
|
---|
| 756 |
|
---|
| 757 |
|
---|
| 758 | /** @name Flags for use with DISFormatYasmEx(), DISFormatMasmEx() and DISFormatGasEx().
|
---|
| 759 | * @{
|
---|
| 760 | */
|
---|
| 761 | /** Put the address to the right. */
|
---|
| 762 | #define DIS_FMT_FLAGS_ADDR_RIGHT RT_BIT_32(0)
|
---|
| 763 | /** Put the address to the left. */
|
---|
| 764 | #define DIS_FMT_FLAGS_ADDR_LEFT RT_BIT_32(1)
|
---|
| 765 | /** Put the address in comments.
|
---|
| 766 | * For some assemblers this implies placing it to the right. */
|
---|
| 767 | #define DIS_FMT_FLAGS_ADDR_COMMENT RT_BIT_32(2)
|
---|
| 768 | /** Put the instruction bytes to the right of the disassembly. */
|
---|
| 769 | #define DIS_FMT_FLAGS_BYTES_RIGHT RT_BIT_32(3)
|
---|
| 770 | /** Put the instruction bytes to the left of the disassembly. */
|
---|
| 771 | #define DIS_FMT_FLAGS_BYTES_LEFT RT_BIT_32(4)
|
---|
| 772 | /** Put the instruction bytes in comments.
|
---|
| 773 | * For some assemblers this implies placing the bytes to the right. */
|
---|
| 774 | #define DIS_FMT_FLAGS_BYTES_COMMENT RT_BIT_32(5)
|
---|
| 775 | /** Put the bytes in square brackets. */
|
---|
| 776 | #define DIS_FMT_FLAGS_BYTES_BRACKETS RT_BIT_32(6)
|
---|
| 777 | /** Put spaces between the bytes. */
|
---|
| 778 | #define DIS_FMT_FLAGS_BYTES_SPACED RT_BIT_32(7)
|
---|
| 779 | /** Display the relative +/- offset of branch instructions that uses relative addresses,
|
---|
| 780 | * and put the target address in parenthesis. */
|
---|
| 781 | #define DIS_FMT_FLAGS_RELATIVE_BRANCH RT_BIT_32(8)
|
---|
[9271] | 782 | /** Strict assembly. The assembly should, when ever possible, make the
|
---|
| 783 | * assembler reproduce the exact same binary. (Refers to the yasm
|
---|
| 784 | * strict keyword.) */
|
---|
| 785 | #define DIS_FMT_FLAGS_STRICT RT_BIT_32(9)
|
---|
[9266] | 786 | /** Checks if the given flags are a valid combination. */
|
---|
| 787 | #define DIS_FMT_FLAGS_IS_VALID(fFlags) \
|
---|
[9271] | 788 | ( !((fFlags) & ~UINT32_C(0x000003ff)) \
|
---|
[9266] | 789 | && ((fFlags) & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) != (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT) \
|
---|
| 790 | && ( !((fFlags) & DIS_FMT_FLAGS_ADDR_COMMENT) \
|
---|
| 791 | || (fFlags & (DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_LEFT)) ) \
|
---|
| 792 | && ((fFlags) & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) != (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT) \
|
---|
| 793 | && ( !((fFlags) & (DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_BRACKETS)) \
|
---|
| 794 | || (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_LEFT)) ) \
|
---|
| 795 | )
|
---|
| 796 | /** @} */
|
---|
| 797 |
|
---|
[41790] | 798 | DISDECL(size_t) DISFormatYasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
|
---|
| 799 | DISDECL(size_t) DISFormatYasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
|
---|
| 800 | DISDECL(size_t) DISFormatMasm( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
|
---|
| 801 | DISDECL(size_t) DISFormatMasmEx(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
|
---|
| 802 | DISDECL(size_t) DISFormatGas( PCDISSTATE pDis, char *pszBuf, size_t cchBuf);
|
---|
| 803 | DISDECL(size_t) DISFormatGasEx( PCDISSTATE pDis, char *pszBuf, size_t cchBuf, uint32_t fFlags, PFNDISGETSYMBOL pfnGetSymbol, void *pvUser);
|
---|
[9266] | 804 |
|
---|
[41790] | 805 | /** @todo DISAnnotate(PCDISSTATE pDis, char *pszBuf, size_t cchBuf, register
|
---|
| 806 | * reader, memory reader); */
|
---|
[9266] | 807 |
|
---|
[41790] | 808 | DISDECL(bool) DISFormatYasmIsOddEncoding(PDISSTATE pDis);
|
---|
[9266] | 809 |
|
---|
[41501] | 810 |
|
---|
[20374] | 811 | RT_C_DECLS_END
|
---|
[1] | 812 |
|
---|
| 813 | #endif
|
---|
| 814 |
|
---|