| 1 | ;; @file
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| 2 | ;
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| 3 | ; CPUM - CPU Monitor.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 | ; The contents of this file may alternatively be used under the terms
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| 18 | ; of the Common Development and Distribution License Version 1.0
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| 19 | ; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | ; VirtualBox OSE distribution, in which case the provisions of the
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| 21 | ; CDDL are applicable instead of those of the GPL.
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| 22 | ;
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| 23 | ; You may elect to license modified versions of this file under the
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| 24 | ; terms and conditions of either the GPL or the CDDL or both.
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| 25 | ;
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| 26 | ; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 27 | ; Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 28 | ; additional information or have any questions.
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| 29 | ;
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| 30 |
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| 31 | %ifndef __VBox_cpum_mac__
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| 32 | %define __VBox_cpum_mac__
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| 33 |
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| 34 |
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| 35 | ;;
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| 36 | ; Converts the CPUM pointer to CPUMCPU (for the first VMCPU)
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| 37 | ; @param %1 register name
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| 38 | %macro CPUMCPU_FROM_CPUM 1
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| 39 | add %1, [%1 + CPUM.ulOffCPUMCPU]
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| 40 | %endmacro
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| 41 |
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| 42 | ;;
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| 43 | ; Converts the CPUMCPU pointer to CPUM (for the first VMCPU)
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| 44 | ; @param %1 register name
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| 45 | %macro CPUM_FROM_CPUMCPU 1
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| 46 | sub %1, [%1 + CPUMCPU.ulOffCPUM]
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| 47 | %endmacro
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| 48 |
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| 49 | ;;
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| 50 | ; Registers frame.
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| 51 | ; This is used internally in TRPM, VMMSwitcher_GuestToHost_GuestCtx
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| 52 | ; and other places.
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| 53 | struc CPUMCTXCORE
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| 54 | .edi resq 1
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| 55 | .esi resq 1
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| 56 | .ebp resq 1
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| 57 | .eax resq 1
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| 58 | .ebx resq 1
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| 59 | .edx resq 1
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| 60 | .ecx resq 1
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| 61 | .esp resq 1
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| 62 | .lss_esp resd 1
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| 63 | .ss resw 1
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| 64 | .ssPadding resw 1
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| 65 | .gs resw 1
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| 66 | .gsPadding resw 1
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| 67 | .fs resw 1
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| 68 | .fsPadding resw 1
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| 69 | .es resw 1
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| 70 | .esPadding resw 1
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| 71 | .ds resw 1
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| 72 | .dsPadding resw 1
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| 73 | .cs resw 1
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| 74 | .csPadding resw 3
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| 75 | .eflags resq 1
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| 76 | .eip resq 1
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| 77 |
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| 78 | .r8 resq 1
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| 79 | .r9 resq 1
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| 80 | .r10 resq 1
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| 81 | .r11 resq 1
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| 82 | .r12 resq 1
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| 83 | .r13 resq 1
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| 84 | .r14 resq 1
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| 85 | .r15 resq 1
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| 86 |
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| 87 | .esHid.u64Base resq 1
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| 88 | .esHid.u32Limit resd 1
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| 89 | .esHid.Attr resd 1
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| 90 |
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| 91 | .csHid.u64Base resq 1
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| 92 | .csHid.u32Limit resd 1
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| 93 | .csHid.Attr resd 1
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| 94 |
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| 95 | .ssHid.u64Base resq 1
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| 96 | .ssHid.u32Limit resd 1
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| 97 | .ssHid.Attr resd 1
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| 98 |
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| 99 | .dsHid.u64Base resq 1
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| 100 | .dsHid.u32Limit resd 1
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| 101 | .dsHid.Attr resd 1
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| 102 |
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| 103 | .fsHid.u64Base resq 1
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| 104 | .fsHid.u32Limit resd 1
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| 105 | .fsHid.Attr resd 1
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| 106 |
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| 107 | .gsHid.u64Base resq 1
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| 108 | .gsHid.u32Limit resd 1
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| 109 | .gsHid.Attr resd 1
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| 110 |
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| 111 | endstruc
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| 112 |
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| 113 |
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| 114 | struc CPUMCTX
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| 115 | .fpu resb 512
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| 116 |
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| 117 | .edi resq 1
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| 118 | .esi resq 1
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| 119 | .ebp resq 1
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| 120 | .eax resq 1
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| 121 | .ebx resq 1
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| 122 | .edx resq 1
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| 123 | .ecx resq 1
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| 124 | .esp resq 1
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| 125 | .lss_esp resd 1
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| 126 | .ss resw 1
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| 127 | .ssPadding resw 1
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| 128 | .gs resw 1
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| 129 | .gsPadding resw 1
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| 130 | .fs resw 1
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| 131 | .fsPadding resw 1
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| 132 | .es resw 1
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| 133 | .esPadding resw 1
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| 134 | .ds resw 1
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| 135 | .dsPadding resw 1
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| 136 | .cs resw 1
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| 137 | .csPadding resw 3
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| 138 | .eflags resq 1
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| 139 | .eip resq 1
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| 140 |
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| 141 | .r8 resq 1
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| 142 | .r9 resq 1
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| 143 | .r10 resq 1
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| 144 | .r11 resq 1
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| 145 | .r12 resq 1
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| 146 | .r13 resq 1
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| 147 | .r14 resq 1
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| 148 | .r15 resq 1
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| 149 |
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| 150 | .esHid.u64Base resq 1
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| 151 | .esHid.u32Limit resd 1
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| 152 | .esHid.Attr resd 1
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| 153 |
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| 154 | .csHid.u64Base resq 1
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| 155 | .csHid.u32Limit resd 1
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| 156 | .csHid.Attr resd 1
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| 157 |
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| 158 | .ssHid.u64Base resq 1
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| 159 | .ssHid.u32Limit resd 1
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| 160 | .ssHid.Attr resd 1
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| 161 |
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| 162 | .dsHid.u64Base resq 1
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| 163 | .dsHid.u32Limit resd 1
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| 164 | .dsHid.Attr resd 1
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| 165 |
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| 166 | .fsHid.u64Base resq 1
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| 167 | .fsHid.u32Limit resd 1
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| 168 | .fsHid.Attr resd 1
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| 169 |
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| 170 | .gsHid.u64Base resq 1
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| 171 | .gsHid.u32Limit resd 1
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| 172 | .gsHid.Attr resd 1
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| 173 |
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| 174 |
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| 175 | .cr0 resq 1
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| 176 | .cr2 resq 1
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| 177 | .cr3 resq 1
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| 178 | .cr4 resq 1
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| 179 |
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| 180 | .dr resq 8
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| 181 |
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| 182 | .gdtr resb 10 ; GDT limit + linear address
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| 183 | .gdtrPadding resw 1
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| 184 | .idtr resb 10 ; IDT limit + linear address
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| 185 | .idtrPadding resw 1
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| 186 | .ldtr resw 1
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| 187 | .ldtrPadding resw 1
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| 188 | .tr resw 1
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| 189 | .trPadding resw 1
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| 190 |
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| 191 | .SysEnter.cs resb 8
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| 192 | .SysEnter.eip resb 8
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| 193 | .SysEnter.esp resb 8
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| 194 |
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| 195 | .msrEFER resb 8
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| 196 | .msrSTAR resb 8
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| 197 | .msrPAT resb 8
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| 198 | .msrLSTAR resb 8
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| 199 | .msrCSTAR resb 8
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| 200 | .msrSFMASK resb 8
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| 201 | .msrKERNELGSBASE resb 8
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| 202 |
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| 203 | .ldtrHid.u64Base resq 1
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| 204 | .ldtrHid.u32Limit resd 1
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| 205 | .ldtrHid.Attr resd 1
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| 206 |
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| 207 | .trHid.u64Base resq 1
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| 208 | .trHid.u32Limit resd 1
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| 209 | .trHid.Attr resd 1
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| 210 |
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| 211 | ; padding
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| 212 | ;;; .padding resd 6
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| 213 | endstruc
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| 214 |
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| 215 | ;;
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| 216 | ; FPU/XMM state
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| 217 | ;;
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| 218 | struc X86FXSTATE
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| 219 | ;/** Control word. */
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| 220 | .FCW resw 1
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| 221 | ;/** Status word. */
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| 222 | .FSW resw 1
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| 223 | ;/** Tag word (it's a byte actually). */
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| 224 | .FTW resb 1
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| 225 | .huh1 resb 1
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| 226 | ;/** Opcode. */
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| 227 | .FOP resw 1
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| 228 | ;/** Instruction pointer. */
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| 229 | .FPUIP resd 1
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| 230 | ;/** Code selector. */
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| 231 | .CS resw 1
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| 232 | .Rsvrd1 resw 1
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| 233 | ;/* - offset 16 - */
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| 234 | ;/** Data pointer. */
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| 235 | .FPUDP resd 1
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| 236 | ;/** Data segment */
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| 237 | .DS resw 1
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| 238 | .Rsrvd2 resw 1
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| 239 | .MXCSR resd 1
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| 240 | .MXCSR_MASK resd 1
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| 241 | ;/* - offset 32 - */
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| 242 | ; FPU & MMX registers
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| 243 | .aRegs resq 8*2
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| 244 | ;/* - offset 160 - */
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| 245 | ;/* 8 XMM registers in 32 bits mode; 16 in long mode */
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| 246 | .aXMM resq 16*2
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| 247 | ;/* - offset 416 - */
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| 248 | .au32RsrvdRest resd (512 - 416) / 4
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| 249 | endstruc
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| 250 |
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| 251 | %endif
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