VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 9013

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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 *
16 * The contents of this file may alternatively be used under the terms
17 * of the Common Development and Distribution License Version 1.0
18 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19 * VirtualBox OSE distribution, in which case the provisions of the
20 * CDDL are applicable instead of those of the GPL.
21 *
22 * You may elect to license modified versions of this file under the
23 * terms and conditions of either the GPL or the CDDL or both.
24 *
25 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26 * Clara, CA 95054 USA or visit http://www.sun.com if you need
27 * additional information or have any questions.
28 */
29
30#ifndef ___VBox_cpum_h
31#define ___VBox_cpum_h
32
33#include <VBox/cdefs.h>
34#include <VBox/types.h>
35#include <VBox/x86.h>
36
37
38__BEGIN_DECLS
39
40/** @defgroup grp_cpum The CPU Monitor(/Manager) API
41 * @{
42 */
43
44/**
45 * Selector hidden registers.
46 */
47typedef struct CPUMSELREGHID
48{
49 /** Base register. */
50 uint32_t u32Base;
51 /** Limit (expanded). */
52 uint32_t u32Limit;
53 /** Flags.
54 * This is the high 32-bit word of the descriptor entry.
55 * Only the flags, dpl and type are used. */
56 X86DESCATTR Attr;
57} CPUMSELREGHID;
58
59
60/**
61 * The sysenter register set.
62 */
63typedef struct CPUMSYSENTER
64{
65 /** Ring 0 cs.
66 * This value + 8 is the Ring 0 ss.
67 * This value + 16 is the Ring 3 cs.
68 * This value + 24 is the Ring 3 ss.
69 */
70 uint64_t cs;
71 /** Ring 0 eip. */
72 uint64_t eip;
73 /** Ring 0 esp. */
74 uint64_t esp;
75} CPUMSYSENTER;
76
77
78/**
79 * CPU context core.
80 */
81#pragma pack(1)
82typedef struct CPUMCTXCORE
83{
84 union
85 {
86 uint32_t edi;
87 uint64_t rdi;
88 };
89 union
90 {
91 uint32_t esi;
92 uint64_t rsi;
93 };
94 union
95 {
96 uint32_t ebp;
97 uint64_t rbp;
98 };
99 union
100 {
101 uint32_t eax;
102 uint64_t rax;
103 };
104 union
105 {
106 uint32_t ebx;
107 uint64_t rbx;
108 };
109 union
110 {
111 uint32_t edx;
112 uint64_t rdx;
113 };
114 union
115 {
116 uint32_t ecx;
117 uint64_t rcx;
118 };
119 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
120 uint32_t esp;
121 RTSEL ss;
122 RTSEL ssPadding;
123 /* Note: no overlap with esp here. */
124 uint64_t rsp;
125
126 RTSEL gs;
127 RTSEL gsPadding;
128 RTSEL fs;
129 RTSEL fsPadding;
130 RTSEL es;
131 RTSEL esPadding;
132 RTSEL ds;
133 RTSEL dsPadding;
134 RTSEL cs;
135 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
136
137 union
138 {
139 X86EFLAGS eflags;
140 X86RFLAGS rflags;
141 };
142 union
143 {
144 uint32_t eip;
145 uint64_t rip;
146 };
147
148 uint64_t r8;
149 uint64_t r9;
150 uint64_t r10;
151 uint64_t r11;
152 uint64_t r12;
153 uint64_t r13;
154 uint64_t r14;
155 uint64_t r15;
156
157 /** Hidden selector registers.
158 * @{ */
159 CPUMSELREGHID esHid;
160 CPUMSELREGHID csHid;
161 CPUMSELREGHID ssHid;
162 CPUMSELREGHID dsHid;
163 CPUMSELREGHID fsHid;
164 CPUMSELREGHID gsHid;
165 /** @} */
166
167} CPUMCTXCORE;
168#pragma pack()
169
170
171/**
172 * CPU context.
173 */
174#pragma pack(1)
175typedef struct CPUMCTX
176{
177 /** FPU state. (16-byte alignment)
178 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
179 * actual format or convert it (waste of time). */
180 X86FXSTATE fpu;
181
182 /** CPUMCTXCORE Part.
183 * @{ */
184 union
185 {
186 uint32_t edi;
187 uint64_t rdi;
188 };
189 union
190 {
191 uint32_t esi;
192 uint64_t rsi;
193 };
194 union
195 {
196 uint32_t ebp;
197 uint64_t rbp;
198 };
199 union
200 {
201 uint32_t eax;
202 uint64_t rax;
203 };
204 union
205 {
206 uint32_t ebx;
207 uint64_t rbx;
208 };
209 union
210 {
211 uint32_t edx;
212 uint64_t rdx;
213 };
214 union
215 {
216 uint32_t ecx;
217 uint64_t rcx;
218 };
219 /* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
220 uint32_t esp;
221 RTSEL ss;
222 RTSEL ssPadding;
223 /* Note: no overlap with esp here. */
224 uint64_t rsp;
225
226 RTSEL gs;
227 RTSEL gsPadding;
228 RTSEL fs;
229 RTSEL fsPadding;
230 RTSEL es;
231 RTSEL esPadding;
232 RTSEL ds;
233 RTSEL dsPadding;
234 RTSEL cs;
235 RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
236
237 union
238 {
239 X86EFLAGS eflags;
240 X86RFLAGS rflags;
241 };
242 union
243 {
244 uint32_t eip;
245 uint64_t rip;
246 };
247
248 uint64_t r8;
249 uint64_t r9;
250 uint64_t r10;
251 uint64_t r11;
252 uint64_t r12;
253 uint64_t r13;
254 uint64_t r14;
255 uint64_t r15;
256
257 /** Hidden selector registers.
258 * @{ */
259 CPUMSELREGHID esHid;
260 CPUMSELREGHID csHid;
261 CPUMSELREGHID ssHid;
262 CPUMSELREGHID dsHid;
263 CPUMSELREGHID fsHid;
264 CPUMSELREGHID gsHid;
265 /** @} */
266
267 /** @} */
268
269 /** Control registers.
270 * @{ */
271 uint64_t cr0;
272 uint64_t cr2;
273 uint64_t cr3;
274 uint64_t cr4;
275 uint64_t cr8;
276 /** @} */
277
278 /** Debug registers.
279 * @{ */
280 uint64_t dr0;
281 uint64_t dr1;
282 uint64_t dr2;
283 uint64_t dr3;
284 uint64_t dr4; /**< @todo remove dr4 and dr5. */
285 uint64_t dr5;
286 uint64_t dr6;
287 uint64_t dr7;
288 /* DR8-15 are currently not supported */
289 /** @} */
290
291 /** Global Descriptor Table register. */
292 VBOXGDTR gdtr;
293 uint16_t gdtrPadding;
294 uint32_t gdtrPadding64;/** @todo fix this hack */
295 /** Interrupt Descriptor Table register. */
296 VBOXIDTR idtr;
297 uint16_t idtrPadding;
298 uint32_t idtrPadding64;/** @todo fix this hack */
299 /** The task register.
300 * Only the guest context uses all the members. */
301 RTSEL ldtr;
302 RTSEL ldtrPadding;
303 /** The task register.
304 * Only the guest context uses all the members. */
305 RTSEL tr;
306 RTSEL trPadding;
307
308 /** The sysenter msr registers.
309 * This member is not used by the hypervisor context. */
310 CPUMSYSENTER SysEnter;
311
312 /** System MSRs.
313 * @{ */
314 uint64_t msrEFER;
315 uint64_t msrSTAR;
316 uint64_t msrPAT;
317 uint64_t msrLSTAR;
318 uint64_t msrCSTAR;
319 uint64_t msrSFMASK;
320 uint64_t msrFSBASE;
321 uint64_t msrGSBASE;
322 uint64_t msrKERNELGSBASE;
323 /** @} */
324
325 /** Hidden selector registers.
326 * @{ */
327 CPUMSELREGHID ldtrHid;
328 CPUMSELREGHID trHid;
329 /** @} */
330
331 /* padding to get 32byte aligned size */
332 uint32_t padding[2];
333} CPUMCTX;
334#pragma pack()
335
336/**
337 * Gets the CPUMCTXCORE part of a CPUMCTX.
338 */
339#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
340
341/**
342 * The register set returned by a CPUID operation.
343 */
344typedef struct CPUMCPUID
345{
346 uint32_t eax;
347 uint32_t ebx;
348 uint32_t ecx;
349 uint32_t edx;
350} CPUMCPUID;
351/** Pointer to a CPUID leaf. */
352typedef CPUMCPUID *PCPUMCPUID;
353/** Pointer to a const CPUID leaf. */
354typedef const CPUMCPUID *PCCPUMCPUID;
355
356/**
357 * CPUID feature to set or clear.
358 */
359typedef enum CPUMCPUIDFEATURE
360{
361 CPUMCPUIDFEATURE_INVALID = 0,
362 /** The APIC feature bit. (Std+Ext) */
363 CPUMCPUIDFEATURE_APIC,
364 /** The sysenter/sysexit feature bit. (Std+Ext) */
365 CPUMCPUIDFEATURE_SEP,
366 /** The PAE feature bit. (Std+Ext) */
367 CPUMCPUIDFEATURE_PAE,
368 /** The LONG MODE feature bit. (Ext) */
369 CPUMCPUIDFEATURE_LONG_MODE
370} CPUMCPUIDFEATURE;
371
372
373/** @name Guest Register Getters.
374 * @{ */
375CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
376CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
377CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
378CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
379CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM);
380CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM);
381CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM);
382CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM);
383CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue);
384CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
385CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
386CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
387CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
388CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
389CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
390CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
391CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
392CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
393CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
394CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
395CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
396CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
397CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
398CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
399CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
400CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
401CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
402CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
403CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
404CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
405CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
406CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
407CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
408CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
409CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
410CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM);
411CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
412CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
413CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
414CPUMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
415CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
416CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
417/** @} */
418
419/** @name Guest Register Setters.
420 * @{ */
421CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
422CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
423CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
424CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
425CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint64_t cr0);
426CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2);
427CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3);
428CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4);
429CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
430CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
431CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
432CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
433CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
434CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
435CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
436CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
437CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
438CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
439CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
440CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
441CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
442CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
443CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
444CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
445CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
446CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
447CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
448CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
449CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
450CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
451CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
452CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
453CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
454CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
455CPUMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
456CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
457/** @} */
458
459/** @name Misc Guest Predicate Functions.
460 * @{ */
461
462/**
463 * Tests if the guest is running in real mode or not.
464 *
465 * @returns true if in real mode, otherwise false.
466 * @param pVM The VM handle.
467 */
468DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
469{
470 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
471}
472
473/**
474 * Tests if the guest is running in protected or not.
475 *
476 * @returns true if in protected mode, otherwise false.
477 * @param pVM The VM handle.
478 */
479DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
480{
481 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
482}
483
484/**
485 * Tests if the guest is running in paged protected or not.
486 *
487 * @returns true if in paged protected mode, otherwise false.
488 * @param pVM The VM handle.
489 */
490DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
491{
492 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
493}
494
495/**
496 * Tests if the guest is running in paged protected or not.
497 *
498 * @returns true if in paged protected mode, otherwise false.
499 * @param pVM The VM handle.
500 */
501CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
502
503/**
504 * Tests if the guest is running in paged protected or not.
505 *
506 * @returns true if in paged protected mode, otherwise false.
507 * @param pVM The VM handle.
508 */
509CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
510
511/**
512 * Tests if the guest is running in paged protected or not.
513 *
514 * @returns true if in paged protected mode, otherwise false.
515 * @param pVM The VM handle.
516 */
517CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
518
519/** @} */
520
521
522
523/** @name Hypervisor Register Getters.
524 * @{ */
525CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
526CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
527CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
528CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
529CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
530CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
531#if 0 /* these are not correct. */
532CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
533CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
534CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
535CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
536#endif
537/** This register is only saved on fatal traps. */
538CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
539CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
540/** This register is only saved on fatal traps. */
541CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
542/** This register is only saved on fatal traps. */
543CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
544CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
545CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
546CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
547CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
548CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
549CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
550CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
551CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
552CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
553CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
554CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
555CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
556CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
557CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
558CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
559CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
560/** @} */
561
562/** @name Hypervisor Register Setters.
563 * @{ */
564CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
565CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
566CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
567CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
568CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
569CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
570CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
571CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
572CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
573CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
574CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
575CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
576CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
577CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
578CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
579CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
580CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
581CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
582CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
583CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
584CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
585CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
586/** @} */
587
588CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
589
590/**
591 * Sets or resets an alternative hypervisor context core.
592 *
593 * This is called when we get a hypervisor trap set switch the context
594 * core with the trap frame on the stack. It is called again to reset
595 * back to the default context core when resuming hypervisor execution.
596 *
597 * @param pVM The VM handle.
598 * @param pCtxCore Pointer to the alternative context core or NULL
599 * to go back to the default context core.
600 */
601CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
602
603
604/**
605 * Queries the pointer to the internal CPUMCTX structure
606 *
607 * @returns VBox status code.
608 * @param pVM Handle to the virtual machine.
609 * @param ppCtx Receives the CPUMCTX pointer when successful.
610 */
611CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
612
613/**
614 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
615 *
616 * @returns VBox status code.
617 * @param pVM Handle to the virtual machine.
618 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
619 */
620CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
621
622
623/**
624 * Gets the pointer to the internal CPUMCTXCORE structure.
625 * This is only for reading in order to save a few calls.
626 *
627 * @param pVM Handle to the virtual machine.
628 */
629CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
630
631/**
632 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
633 * This is only for reading in order to save a few calls.
634 *
635 * @param pVM Handle to the virtual machine.
636 */
637CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
638
639/**
640 * Sets the guest context core registers.
641 *
642 * @param pVM Handle to the virtual machine.
643 * @param pCtxCore The new context core values.
644 */
645CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
646
647
648/**
649 * Transforms the guest CPU state to raw-ring mode.
650 *
651 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
652 *
653 * @returns VBox status. (recompiler failure)
654 * @param pVM VM handle.
655 * @param pCtxCore The context core (for trap usage).
656 * @see @ref pg_raw
657 */
658CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
659
660/**
661 * Transforms the guest CPU state from raw-ring mode to correct values.
662 *
663 * This function will change any selector registers with DPL=1 to DPL=0.
664 *
665 * @returns Adjusted rc.
666 * @param pVM VM handle.
667 * @param rc Raw mode return code
668 * @param pCtxCore The context core (for trap usage).
669 * @see @ref pg_raw
670 */
671CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
672
673/**
674 * Gets the EFLAGS while we're in raw-mode.
675 *
676 * @returns The eflags.
677 * @param pVM The VM handle.
678 * @param pCtxCore The context core.
679 */
680CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
681
682/**
683 * Updates the EFLAGS while we're in raw-mode.
684 *
685 * @param pVM The VM handle.
686 * @param pCtxCore The context core.
687 * @param eflags The new EFLAGS value.
688 */
689CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
690
691/**
692 * Lazily sync in the FPU/XMM state
693 *
694 * This function will change any selector registers with DPL=1 to DPL=0.
695 *
696 * @returns VBox status code.
697 * @param pVM VM handle.
698 */
699CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
700
701
702/**
703 * Restore host FPU/XMM state
704 *
705 * @returns VBox status code.
706 * @param pVM VM handle.
707 */
708CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
709
710/** @name Changed flags
711 * These flags are used to keep track of which important register that
712 * have been changed since last they were reset. The only one allowed
713 * to clear them is REM!
714 * @{
715 */
716#define CPUM_CHANGED_FPU_REM RT_BIT(0)
717#define CPUM_CHANGED_CR0 RT_BIT(1)
718#define CPUM_CHANGED_CR4 RT_BIT(2)
719#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
720#define CPUM_CHANGED_CR3 RT_BIT(4)
721#define CPUM_CHANGED_GDTR RT_BIT(5)
722#define CPUM_CHANGED_IDTR RT_BIT(6)
723#define CPUM_CHANGED_LDTR RT_BIT(7)
724#define CPUM_CHANGED_TR RT_BIT(8)
725#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
726#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
727#define CPUM_CHANGED_CPUID RT_BIT(11)
728/** @} */
729
730/**
731 * Gets and resets the changed flags (CPUM_CHANGED_*).
732 *
733 * @returns The changed flags.
734 * @param pVM VM handle.
735 */
736CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
737
738/**
739 * Sets the specified changed flags (CPUM_CHANGED_*).
740 *
741 * @param pVM The VM handle.
742 */
743CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
744
745/**
746 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
747 * @returns true if supported.
748 * @returns false if not supported.
749 * @param pVM The VM handle.
750 */
751CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
752
753/**
754 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
755 * @returns true if used.
756 * @returns false if not used.
757 * @param pVM The VM handle.
758 */
759CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
760
761/**
762 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
763 * @returns true if used.
764 * @returns false if not used.
765 * @param pVM The VM handle.
766 */
767CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
768
769/**
770 * Checks if we activated the FPU/XMM state of the guest OS
771 * @returns true if we did.
772 * @returns false if not.
773 * @param pVM The VM handle.
774 */
775CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
776
777/**
778 * Deactivate the FPU/XMM state of the guest OS
779 * @param pVM The VM handle.
780 */
781CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
782
783
784/**
785 * Checks if the hidden selector registers are valid
786 * @returns true if they are.
787 * @returns false if not.
788 * @param pVM The VM handle.
789 */
790CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
791
792/**
793 * Checks if the hidden selector registers are valid
794 * @param pVM The VM handle.
795 * @param fValid Valid or not
796 */
797CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
798
799/**
800 * Get the current privilege level of the guest.
801 *
802 * @returns cpl
803 * @param pVM VM Handle.
804 * @param pRegFrame Trap register frame.
805 */
806CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
807
808/**
809 * CPU modes.
810 */
811typedef enum CPUMMODE
812{
813 /** The usual invalid zero entry. */
814 CPUMMODE_INVALID = 0,
815 /** Real mode. */
816 CPUMMODE_REAL,
817 /** Protected mode (32-bit). */
818 CPUMMODE_PROTECTED,
819 /** Long mode (64-bit). */
820 CPUMMODE_LONG
821} CPUMMODE;
822
823/**
824 * Gets the current guest CPU mode.
825 *
826 * If paging mode is what you need, check out PGMGetGuestMode().
827 *
828 * @returns The CPU mode.
829 * @param pVM The VM handle.
830 */
831CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
832
833
834#ifdef IN_RING3
835/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
836 * @ingroup grp_cpum
837 * @{
838 */
839
840/**
841 * Initializes the CPUM.
842 *
843 * @returns VBox status code.
844 * @param pVM The VM to operate on.
845 */
846CPUMR3DECL(int) CPUMR3Init(PVM pVM);
847
848/**
849 * Applies relocations to data and code managed by this
850 * component. This function will be called at init and
851 * whenever the VMM need to relocate it self inside the GC.
852 *
853 * The CPUM will update the addresses used by the switcher.
854 *
855 * @param pVM The VM.
856 */
857CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
858
859/**
860 * Terminates the CPUM.
861 *
862 * Termination means cleaning up and freeing all resources,
863 * the VM it self is at this point powered off or suspended.
864 *
865 * @returns VBox status code.
866 * @param pVM The VM to operate on.
867 */
868CPUMR3DECL(int) CPUMR3Term(PVM pVM);
869
870/**
871 * Resets the CPU.
872 *
873 * @param pVM The VM handle.
874 */
875CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
876
877/**
878 * Queries the pointer to the internal CPUMCTX structure
879 *
880 * @returns VBox status code.
881 * @param pVM Handle to the virtual machine.
882 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
883 */
884CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
885
886
887#ifdef DEBUG
888/**
889 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
890 *
891 * @internal
892 */
893CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
894#endif
895
896/**
897 * API for controlling a few of the CPU features found in CR4.
898 *
899 * Currently only X86_CR4_TSD is accepted as input.
900 *
901 * @returns VBox status code.
902 *
903 * @param pVM The VM handle.
904 * @param fOr The CR4 OR mask.
905 * @param fAnd The CR4 AND mask.
906 */
907CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
908
909/** @} */
910#endif
911
912#ifdef IN_GC
913/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
914 * @ingroup grp_cpum
915 * @{
916 */
917
918/**
919 * Calls a guest trap/interrupt handler directly
920 * Assumes a trap stack frame has already been setup on the guest's stack!
921 *
922 * @param pRegFrame Original trap/interrupt context
923 * @param selCS Code selector of handler
924 * @param pHandler GC virtual address of handler
925 * @param eflags Callee's EFLAGS
926 * @param selSS Stack selector for handler
927 * @param pEsp Stack address for handler
928 *
929 * This function does not return!
930 *
931 */
932DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
933
934/**
935 * Performs an iret to V86 code
936 * Assumes a trap stack frame has already been setup on the guest's stack!
937 *
938 * @param pRegFrame Original trap/interrupt context
939 *
940 * This function does not return!
941 */
942CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
943
944/** @} */
945#endif
946
947#ifdef IN_RING0
948/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
949 * @ingroup grp_cpum
950 * @{
951 */
952
953/**
954 * Does Ring-0 CPUM initialization.
955 *
956 * This is mainly to check that the Host CPU mode is compatible
957 * with VBox.
958 *
959 * @returns VBox status code.
960 * @param pVM The VM to operate on.
961 */
962CPUMR0DECL(int) CPUMR0Init(PVM pVM);
963
964/** @} */
965#endif
966
967/** @} */
968__END_DECLS
969
970
971#endif
972
973
974
975
976
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