VirtualBox

source: vbox/trunk/include/VBox/cpum.h@ 4506

Last change on this file since 4506 was 4208, checked in by vboxsync, 17 years ago

CPUMGetGuestMode
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1/** @file
2 * CPUM - CPU Monitor(/ Manager).
3 */
4
5/*
6 * Copyright (C) 2006-2007 innotek GmbH
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License as published by the Free Software Foundation,
12 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
13 * distribution. VirtualBox OSE is distributed in the hope that it will
14 * be useful, but WITHOUT ANY WARRANTY of any kind.
15 */
16
17#ifndef ___VBox_cpum_h
18#define ___VBox_cpum_h
19
20#include <VBox/cdefs.h>
21#include <VBox/types.h>
22#include <VBox/x86.h>
23
24
25__BEGIN_DECLS
26
27/** @defgroup grp_cpum The CPU Monitor(/Manager) API
28 * @{
29 */
30
31/**
32 * Selector hidden registers.
33 */
34typedef struct CPUMSELREGHIDDEN
35{
36 /** Base register. */
37 uint32_t u32Base;
38 /** Limit (expanded). */
39 uint32_t u32Limit;
40 /** Flags.
41 * This is the high 32-bit word of the descriptor entry.
42 * Only the flags, dpl and type are used. */
43 X86DESCATTR Attr;
44} CPUMSELREGHID;
45/** Pointer to selector hidden registers. */
46typedef CPUMSELREGHID *PCPUMSELREGHID;
47/** Pointer to const selector hidden registers. */
48typedef const CPUMSELREGHID *PCCPUMSELREGHID;
49
50
51/**
52 * The sysenter register set.
53 */
54typedef struct CPUMSYSENTER
55{
56 /** Ring 0 cs.
57 * This value + 8 is the Ring 0 ss.
58 * This value + 16 is the Ring 3 cs.
59 * This value + 24 is the Ring 3 ss.
60 */
61 uint64_t cs;
62 /** Ring 0 eip. */
63 uint64_t eip;
64 /** Ring 0 esp. */
65 uint64_t esp;
66} CPUMSYSENTER;
67
68
69/**
70 * CPU context core.
71 */
72#pragma pack(1)
73typedef struct CPUMCTXCORE
74{
75 uint32_t edi;
76 uint32_t esi;
77 uint32_t ebp;
78 uint32_t eax;
79 uint32_t ebx;
80 uint32_t edx;
81 uint32_t ecx;
82
83 uint32_t esp;
84 RTSEL ss;
85 RTSEL ssPadding;
86
87 RTSEL gs;
88 RTSEL gsPadding;
89 RTSEL fs;
90 RTSEL fsPadding;
91 RTSEL es;
92 RTSEL esPadding;
93 RTSEL ds;
94 RTSEL dsPadding;
95 RTSEL cs;
96 RTSEL csPadding;
97
98 X86EFLAGS eflags;
99 uint32_t eip;
100
101 /** Hidden selector registers.
102 * @{ */
103 CPUMSELREGHID esHid;
104 CPUMSELREGHID csHid;
105 CPUMSELREGHID ssHid;
106 CPUMSELREGHID dsHid;
107 CPUMSELREGHID fsHid;
108 CPUMSELREGHID gsHid;
109 /** @} */
110
111} CPUMCTXCORE;
112/** Pointer to CPU context core. */
113typedef CPUMCTXCORE *PCPUMCTXCORE;
114/** Pointer to const CPU context core. */
115typedef const CPUMCTXCORE *PCCPUMCTXCORE;
116#pragma pack()
117
118/**
119 * CPU context.
120 */
121#pragma pack(1)
122typedef struct CPUMCTX
123{
124 /** FPU state. (16-byte alignment)
125 * @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
126 * actual format or convert it (waste of time). */
127 X86FXSTATE fpu;
128
129 /** CPUMCTXCORE Part.
130 * @{ */
131 uint32_t edi;
132 uint32_t esi;
133 uint32_t ebp;
134 uint32_t eax;
135 uint32_t ebx;
136 uint32_t edx;
137 uint32_t ecx;
138
139 uint32_t esp;
140 RTSEL ss;
141 RTSEL ssPadding;
142
143 RTSEL gs;
144 RTSEL gsPadding;
145 RTSEL fs;
146 RTSEL fsPadding;
147 RTSEL es;
148 RTSEL esPadding;
149 RTSEL ds;
150 RTSEL dsPadding;
151 RTSEL cs;
152 RTSEL csPadding;
153
154 X86EFLAGS eflags;
155 uint32_t eip;
156
157 /** Hidden selector registers.
158 * @{ */
159 CPUMSELREGHID esHid;
160 CPUMSELREGHID csHid;
161 CPUMSELREGHID ssHid;
162 CPUMSELREGHID dsHid;
163 CPUMSELREGHID fsHid;
164 CPUMSELREGHID gsHid;
165 /** @} */
166
167 /** @} */
168
169 /** Control registers.
170 * @{ */
171 uint32_t cr0;
172 uint32_t cr2;
173 uint32_t cr3;
174 uint32_t cr4;
175 /** @} */
176
177 /** Debug registers.
178 * @{ */
179 uint32_t dr0;
180 uint32_t dr1;
181 uint32_t dr2;
182 uint32_t dr3;
183 uint32_t dr4; /**< @todo remove dr4 and dr5. */
184 uint32_t dr5;
185 uint32_t dr6;
186 uint32_t dr7;
187 /** @} */
188
189 /** Global Descriptor Table register. */
190 VBOXGDTR gdtr;
191 uint16_t gdtrPadding;
192 uint32_t gdtrPadding64;/** @todo fix this hack */
193 /** Interrupt Descriptor Table register. */
194 VBOXIDTR idtr;
195 uint16_t idtrPadding;
196 uint32_t idtrPadding64;/** @todo fix this hack */
197 /** The task register.
198 * Only the guest context uses all the members. */
199 RTSEL ldtr;
200 RTSEL ldtrPadding;
201 /** The task register.
202 * Only the guest context uses all the members. */
203 RTSEL tr;
204 RTSEL trPadding;
205
206 /** The sysenter msr registers.
207 * This member is not used by the hypervisor context. */
208 CPUMSYSENTER SysEnter;
209
210 /** Hidden selector registers.
211 * @{ */
212 CPUMSELREGHID ldtrHid;
213 CPUMSELREGHID trHid;
214 /** @} */
215
216 /* padding to get 32byte aligned size */
217 uint32_t padding[6];
218} CPUMCTX;
219#pragma pack()
220/** Pointer to CPUMCTX. */
221typedef CPUMCTX *PCPUMCTX;
222
223/**
224 * Gets the CPUMCTXCORE part of a CPUMCTX.
225 */
226#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
227
228/**
229 * The register set returned by a CPUID operation.
230 */
231typedef struct CPUMCPUID
232{
233 uint32_t eax;
234 uint32_t ebx;
235 uint32_t ecx;
236 uint32_t edx;
237} CPUMCPUID;
238/** Pointer to a CPUID leaf. */
239typedef CPUMCPUID *PCPUMCPUID;
240/** Pointer to a const CPUID leaf. */
241typedef const CPUMCPUID *PCCPUMCPUID;
242
243/**
244 * CPUID feature to set or clear.
245 */
246typedef enum CPUMCPUIDFEATURE
247{
248 CPUMCPUIDFEATURE_INVALID = 0,
249 /** The APIC feature bit. (Std+Ext) */
250 CPUMCPUIDFEATURE_APIC,
251 /** The sysenter/sysexit feature bit. (Std+Ext) */
252 CPUMCPUIDFEATURE_SEP
253} CPUMCPUIDFEATURE;
254
255
256/** @name Guest Register Getters.
257 * @{ */
258CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
259CPUMDECL(uint32_t) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
260CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
261CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
262CPUMDECL(uint32_t) CPUMGetGuestCR0(PVM pVM);
263CPUMDECL(uint32_t) CPUMGetGuestCR2(PVM pVM);
264CPUMDECL(uint32_t) CPUMGetGuestCR3(PVM pVM);
265CPUMDECL(uint32_t) CPUMGetGuestCR4(PVM pVM);
266CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
267CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
268CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
269CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
270CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
271CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
272CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
273CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
274CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
275CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
276CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
277CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
278CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
279CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
280CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
281CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
282CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
283CPUMDECL(RTUINTREG) CPUMGetGuestDR0(PVM pVM);
284CPUMDECL(RTUINTREG) CPUMGetGuestDR1(PVM pVM);
285CPUMDECL(RTUINTREG) CPUMGetGuestDR2(PVM pVM);
286CPUMDECL(RTUINTREG) CPUMGetGuestDR3(PVM pVM);
287CPUMDECL(RTUINTREG) CPUMGetGuestDR6(PVM pVM);
288CPUMDECL(RTUINTREG) CPUMGetGuestDR7(PVM pVM);
289CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint32_t *pValue);
290CPUMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
291CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdGCPtr(PVM pVM);
292CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM);
293CPUMDECL(GCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM);
294CPUMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
295CPUMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
296CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
297/** @} */
298
299/** @name Guest Register Setters.
300 * @{ */
301CPUMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
302CPUMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
303CPUMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
304CPUMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
305CPUMDECL(int) CPUMSetGuestCR0(PVM pVM, uint32_t cr0);
306CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint32_t cr2);
307CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint32_t cr3);
308CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint32_t cr4);
309CPUMDECL(int) CPUMSetGuestCRx(PVM pVM, uint32_t iReg, uint32_t Value);
310CPUMDECL(int) CPUMSetGuestDR0(PVM pVM, RTGCUINTREG uDr0);
311CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, RTGCUINTREG uDr1);
312CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, RTGCUINTREG uDr2);
313CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, RTGCUINTREG uDr3);
314CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, RTGCUINTREG uDr6);
315CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, RTGCUINTREG uDr7);
316CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint32_t Value);
317CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
318CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
319CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
320CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
321CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
322CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
323CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
324CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
325CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
326CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
327CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
328CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
329CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
330CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
331CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
332CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
333CPUMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
334CPUMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
335CPUMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
336/** @} */
337
338/** @name Misc Guest Predicate Functions.
339 * @{ */
340
341/**
342 * Tests if the guest is running in real mode or not.
343 *
344 * @returns true if in real mode, otherwise false.
345 * @param pVM The VM handle.
346 */
347DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
348{
349 return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
350}
351
352/**
353 * Tests if the guest is running in protected or not.
354 *
355 * @returns true if in protected mode, otherwise false.
356 * @param pVM The VM handle.
357 */
358DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
359{
360 return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
361}
362
363/**
364 * Tests if the guest is running in paged protected or not.
365 *
366 * @returns true if in paged protected mode, otherwise false.
367 * @param pVM The VM handle.
368 */
369DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
370{
371 return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
372}
373
374/**
375 * Tests if the guest is running in paged protected or not.
376 *
377 * @returns true if in paged protected mode, otherwise false.
378 * @param pVM The VM handle.
379 */
380CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
381
382/**
383 * Tests if the guest is running in paged protected or not.
384 *
385 * @returns true if in paged protected mode, otherwise false.
386 * @param pVM The VM handle.
387 */
388CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
389
390/**
391 * Tests if the guest is running in paged protected or not.
392 *
393 * @returns true if in paged protected mode, otherwise false.
394 * @param pVM The VM handle.
395 */
396CPUMDECL(bool) CPUMIsGuestIn64BitCode(PVM pVM);
397
398/** @} */
399
400
401
402/** @name Hypervisor Register Getters.
403 * @{ */
404CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
405CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
406CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
407CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
408CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
409CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
410#if 0 /* these are not correct. */
411CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
412CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
413CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
414CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
415#endif
416/** This register is only saved on fatal traps. */
417CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
418CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
419/** This register is only saved on fatal traps. */
420CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
421/** This register is only saved on fatal traps. */
422CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
423CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
424CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
425CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
426CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
427CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
428CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
429CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
430CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
431CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
432CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
433CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
434CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
435CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
436CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
437CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
438CPUMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
439/** @} */
440
441/** @name Hypervisor Register Setters.
442 * @{ */
443CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
444CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
445CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
446CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
447CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
448CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
449CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
450CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
451CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
452CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
453CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
454CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
455CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
456CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
457CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
458CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
459CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
460CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
461CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
462CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
463CPUMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
464CPUMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
465/** @} */
466
467CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
468
469/**
470 * Sets or resets an alternative hypervisor context core.
471 *
472 * This is called when we get a hypervisor trap set switch the context
473 * core with the trap frame on the stack. It is called again to reset
474 * back to the default context core when resuming hypervisor execution.
475 *
476 * @param pVM The VM handle.
477 * @param pCtxCore Pointer to the alternative context core or NULL
478 * to go back to the default context core.
479 */
480CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
481
482
483/**
484 * Queries the pointer to the internal CPUMCTX structure
485 *
486 * @returns VBox status code.
487 * @param pVM Handle to the virtual machine.
488 * @param ppCtx Receives the CPUMCTX pointer when successful.
489 */
490CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
491
492/**
493 * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
494 *
495 * @returns VBox status code.
496 * @param pVM Handle to the virtual machine.
497 * @param ppCtx Receives the hyper CPUMCTX pointer when successful.
498 */
499CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
500
501
502/**
503 * Gets the pointer to the internal CPUMCTXCORE structure.
504 * This is only for reading in order to save a few calls.
505 *
506 * @param pVM Handle to the virtual machine.
507 */
508CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
509
510/**
511 * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
512 * This is only for reading in order to save a few calls.
513 *
514 * @param pVM Handle to the virtual machine.
515 */
516CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
517
518/**
519 * Sets the guest context core registers.
520 *
521 * @param pVM Handle to the virtual machine.
522 * @param pCtxCore The new context core values.
523 */
524CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
525
526
527/**
528 * Transforms the guest CPU state to raw-ring mode.
529 *
530 * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
531 *
532 * @returns VBox status. (recompiler failure)
533 * @param pVM VM handle.
534 * @param pCtxCore The context core (for trap usage).
535 * @see @ref pg_raw
536 */
537CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
538
539/**
540 * Transforms the guest CPU state from raw-ring mode to correct values.
541 *
542 * This function will change any selector registers with DPL=1 to DPL=0.
543 *
544 * @returns Adjusted rc.
545 * @param pVM VM handle.
546 * @param rc Raw mode return code
547 * @param pCtxCore The context core (for trap usage).
548 * @see @ref pg_raw
549 */
550CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
551
552/**
553 * Gets the EFLAGS while we're in raw-mode.
554 *
555 * @returns The eflags.
556 * @param pVM The VM handle.
557 * @param pCtxCore The context core.
558 */
559CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
560
561/**
562 * Updates the EFLAGS while we're in raw-mode.
563 *
564 * @param pVM The VM handle.
565 * @param pCtxCore The context core.
566 * @param eflags The new EFLAGS value.
567 */
568CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
569
570/**
571 * Lazily sync in the FPU/XMM state
572 *
573 * This function will change any selector registers with DPL=1 to DPL=0.
574 *
575 * @returns VBox status code.
576 * @param pVM VM handle.
577 */
578CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
579
580
581/**
582 * Restore host FPU/XMM state
583 *
584 * @returns VBox status code.
585 * @param pVM VM handle.
586 */
587CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
588
589/** @name Changed flags
590 * These flags are used to keep track of which important register that
591 * have been changed since last they were reset. The only one allowed
592 * to clear them is REM!
593 * @{
594 */
595#define CPUM_CHANGED_FPU_REM BIT(0)
596#define CPUM_CHANGED_CR0 BIT(1)
597#define CPUM_CHANGED_CR4 BIT(2)
598#define CPUM_CHANGED_GLOBAL_TLB_FLUSH BIT(3)
599#define CPUM_CHANGED_CR3 BIT(4)
600#define CPUM_CHANGED_GDTR BIT(5)
601#define CPUM_CHANGED_IDTR BIT(6)
602#define CPUM_CHANGED_LDTR BIT(7)
603#define CPUM_CHANGED_TR BIT(8)
604#define CPUM_CHANGED_SYSENTER_MSR BIT(9)
605#define CPUM_CHANGED_HIDDEN_SEL_REGS BIT(10)
606/** @} */
607
608/**
609 * Gets and resets the changed flags (CPUM_CHANGED_*).
610 *
611 * @returns The changed flags.
612 * @param pVM VM handle.
613 */
614CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
615
616/**
617 * Sets the specified changed flags (CPUM_CHANGED_*).
618 *
619 * @param pVM The VM handle.
620 */
621CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
622
623/**
624 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
625 * @returns true if supported.
626 * @returns false if not supported.
627 * @param pVM The VM handle.
628 */
629CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
630
631/**
632 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
633 * @returns true if used.
634 * @returns false if not used.
635 * @param pVM The VM handle.
636 */
637CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
638
639/**
640 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
641 * @returns true if used.
642 * @returns false if not used.
643 * @param pVM The VM handle.
644 */
645CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
646
647/**
648 * Checks if we activated the FPU/XMM state of the guest OS
649 * @returns true if we did.
650 * @returns false if not.
651 * @param pVM The VM handle.
652 */
653CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
654
655/**
656 * Deactivate the FPU/XMM state of the guest OS
657 * @param pVM The VM handle.
658 */
659CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
660
661
662/**
663 * Checks if the hidden selector registers are valid
664 * @returns true if they are.
665 * @returns false if not.
666 * @param pVM The VM handle.
667 */
668CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
669
670/**
671 * Checks if the hidden selector registers are valid
672 * @param pVM The VM handle.
673 * @param fValid Valid or not
674 */
675CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
676
677/**
678 * Get the current privilege level of the guest.
679 *
680 * @returns cpl
681 * @param pVM VM Handle.
682 * @param pRegFrame Trap register frame.
683 */
684CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
685
686/**
687 * CPU modes.
688 */
689typedef enum CPUMMODE
690{
691 /** The usual invalid zero entry. */
692 CPUMMODE_INVALID = 0,
693 /** Real mode. */
694 CPUMMODE_REAL,
695 /** Protected mode (32-bit). */
696 CPUMMODE_PROTECTED,
697 /** Long mode (64-bit). */
698 CPUMMODE_LONG
699} CPUMMODE;
700
701/**
702 * Gets the current guest CPU mode.
703 *
704 * If paging mode is what you need, check out PGMGetGuestMode().
705 *
706 * @returns The CPU mode.
707 * @param pVM The VM handle.
708 */
709CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
710
711
712#ifdef IN_RING3
713/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
714 * @ingroup grp_cpum
715 * @{
716 */
717
718/**
719 * Initializes the CPUM.
720 *
721 * @returns VBox status code.
722 * @param pVM The VM to operate on.
723 */
724CPUMR3DECL(int) CPUMR3Init(PVM pVM);
725
726/**
727 * Applies relocations to data and code managed by this
728 * component. This function will be called at init and
729 * whenever the VMM need to relocate it self inside the GC.
730 *
731 * The CPUM will update the addresses used by the switcher.
732 *
733 * @param pVM The VM.
734 */
735CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
736
737/**
738 * Terminates the CPUM.
739 *
740 * Termination means cleaning up and freeing all resources,
741 * the VM it self is at this point powered off or suspended.
742 *
743 * @returns VBox status code.
744 * @param pVM The VM to operate on.
745 */
746CPUMR3DECL(int) CPUMR3Term(PVM pVM);
747
748/**
749 * Resets the CPU.
750 *
751 * @param pVM The VM handle.
752 */
753CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
754
755/**
756 * Queries the pointer to the internal CPUMCTX structure
757 *
758 * @returns VBox status code.
759 * @param pVM Handle to the virtual machine.
760 * @param ppCtx Receives the CPUMCTX GC pointer when successful.
761 */
762CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, GCPTRTYPE(PCPUMCTX) *ppCtx);
763
764
765#ifdef DEBUG
766/**
767 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
768 *
769 * @internal
770 */
771CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
772#endif
773
774/**
775 * API for controlling a few of the CPU features found in CR4.
776 *
777 * Currently only X86_CR4_TSD is accepted as input.
778 *
779 * @returns VBox status code.
780 *
781 * @param pVM The VM handle.
782 * @param fOr The CR4 OR mask.
783 * @param fAnd The CR4 AND mask.
784 */
785CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
786
787/** @} */
788#endif
789
790#ifdef IN_GC
791/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
792 * @ingroup grp_cpum
793 * @{
794 */
795
796/**
797 * Calls a guest trap/interrupt handler directly
798 * Assumes a trap stack frame has already been setup on the guest's stack!
799 *
800 * @param pRegFrame Original trap/interrupt context
801 * @param selCS Code selector of handler
802 * @param pHandler GC virtual address of handler
803 * @param eflags Callee's EFLAGS
804 * @param selSS Stack selector for handler
805 * @param pEsp Stack address for handler
806 *
807 * This function does not return!
808 *
809 */
810CPUMGCDECL(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTGCPTR pHandler, uint32_t eflags, uint32_t selSS, RTGCPTR pEsp);
811
812/**
813 * Performs an iret to V86 code
814 * Assumes a trap stack frame has already been setup on the guest's stack!
815 *
816 * @param pRegFrame Original trap/interrupt context
817 *
818 * This function does not return!
819 */
820CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
821
822/** @} */
823#endif
824
825#ifdef IN_RING0
826/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
827 * @ingroup grp_cpum
828 * @{
829 */
830
831/**
832 * Does Ring-0 CPUM initialization.
833 *
834 * This is mainly to check that the Host CPU mode is compatible
835 * with VBox.
836 *
837 * @returns VBox status code.
838 * @param pVM The VM to operate on.
839 */
840CPUMR0DECL(int) CPUMR0Init(PVM pVM);
841
842/** @} */
843#endif
844
845/** @} */
846__END_DECLS
847
848
849#endif
850
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852
853
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