cpum.h@ 14972

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1	/** @file
2	* CPUM - CPU Monitor(/ Manager).
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	#ifndef ___VBox_cpum_h
31	#define ___VBox_cpum_h
32
33	#include <VBox/cdefs.h>
34	#include <VBox/types.h>
35	#include <VBox/x86.h>
36
37
38	__BEGIN_DECLS
39
40	/** @defgroup grp_cpum The CPU Monitor / Manager API
41	* @{
42	*/
43
44	/**
45	* Selector hidden registers.
46	*/
47	typedef struct CPUMSELREGHID
48	{
49	/** Base register.
50	*
51	* Long mode remarks:
52	* - Unused in long mode for CS, DS, ES, SS
53	* - 32 bits for FS & GS; FS(GS)_BASE msr used for the base address
54	* - 64 bits for TR & LDTR
55	*/
56	uint64_t u64Base;
57	/** Limit (expanded). */
58	uint32_t u32Limit;
59	/** Flags.
60	* This is the high 32-bit word of the descriptor entry.
61	* Only the flags, dpl and type are used. */
62	X86DESCATTR Attr;
63	} CPUMSELREGHID;
64
65
66	/**
67	* The sysenter register set.
68	*/
69	typedef struct CPUMSYSENTER
70	{
71	/** Ring 0 cs.
72	* This value + 8 is the Ring 0 ss.
73	* This value + 16 is the Ring 3 cs.
74	* This value + 24 is the Ring 3 ss.
75	*/
76	uint64_t cs;
77	/** Ring 0 eip. */
78	uint64_t eip;
79	/** Ring 0 esp. */
80	uint64_t esp;
81	} CPUMSYSENTER;
82
83
84	/**
85	* CPU context core.
86	*/
87	#pragma pack(1)
88	typedef struct CPUMCTXCORE
89	{
90	union
91	{
92	uint16_t di;
93	uint32_t edi;
94	uint64_t rdi;
95	};
96	union
97	{
98	uint16_t si;
99	uint32_t esi;
100	uint64_t rsi;
101	};
102	union
103	{
104	uint16_t bp;
105	uint32_t ebp;
106	uint64_t rbp;
107	};
108	union
109	{
110	uint16_t ax;
111	uint32_t eax;
112	uint64_t rax;
113	};
114	union
115	{
116	uint16_t bx;
117	uint32_t ebx;
118	uint64_t rbx;
119	};
120	union
121	{
122	uint16_t dx;
123	uint32_t edx;
124	uint64_t rdx;
125	};
126	union
127	{
128	uint16_t cx;
129	uint32_t ecx;
130	uint64_t rcx;
131	};
132	union
133	{
134	uint16_t sp;
135	uint32_t esp;
136	uint64_t rsp;
137	};
138	/* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before. */
139	uint32_t lss_esp;
140	RTSEL ss;
141	RTSEL ssPadding;
142
143	RTSEL gs;
144	RTSEL gsPadding;
145	RTSEL fs;
146	RTSEL fsPadding;
147	RTSEL es;
148	RTSEL esPadding;
149	RTSEL ds;
150	RTSEL dsPadding;
151	RTSEL cs;
152	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
153
154	union
155	{
156	X86EFLAGS eflags;
157	X86RFLAGS rflags;
158	};
159	union
160	{
161	uint16_t ip;
162	uint32_t eip;
163	uint64_t rip;
164	};
165
166	uint64_t r8;
167	uint64_t r9;
168	uint64_t r10;
169	uint64_t r11;
170	uint64_t r12;
171	uint64_t r13;
172	uint64_t r14;
173	uint64_t r15;
174
175	/** Hidden selector registers.
176	* @{ */
177	CPUMSELREGHID esHid;
178	CPUMSELREGHID csHid;
179	CPUMSELREGHID ssHid;
180	CPUMSELREGHID dsHid;
181	CPUMSELREGHID fsHid;
182	CPUMSELREGHID gsHid;
183	/** @} */
184
185	} CPUMCTXCORE;
186	#pragma pack()
187
188
189	/**
190	* CPU context.
191	*/
192	#pragma pack(1)
193	typedef struct CPUMCTX
194	{
195	/** FPU state. (16-byte alignment)
196	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
197	* actual format or convert it (waste of time). */
198	X86FXSTATE fpu;
199
200	/** CPUMCTXCORE Part.
201	* @{ */
202	union
203	{
204	uint16_t di;
205	uint32_t edi;
206	uint64_t rdi;
207	};
208	union
209	{
210	uint16_t si;
211	uint32_t esi;
212	uint64_t rsi;
213	};
214	union
215	{
216	uint16_t bp;
217	uint32_t ebp;
218	uint64_t rbp;
219	};
220	union
221	{
222	uint16_t ax;
223	uint32_t eax;
224	uint64_t rax;
225	};
226	union
227	{
228	uint16_t bx;
229	uint32_t ebx;
230	uint64_t rbx;
231	};
232	union
233	{
234	uint16_t dx;
235	uint32_t edx;
236	uint64_t rdx;
237	};
238	union
239	{
240	uint16_t cx;
241	uint32_t ecx;
242	uint64_t rcx;
243	};
244	union
245	{
246	uint16_t sp;
247	uint32_t esp;
248	uint64_t rsp;
249	};
250	/* Note: lss esp, [] in the switcher needs some space, so we reserve it here instead of relying on the exact esp & ss layout as before (prevented us from using a union with rsp). */
251	uint32_t lss_esp;
252	RTSEL ss;
253	RTSEL ssPadding;
254
255	RTSEL gs;
256	RTSEL gsPadding;
257	RTSEL fs;
258	RTSEL fsPadding;
259	RTSEL es;
260	RTSEL esPadding;
261	RTSEL ds;
262	RTSEL dsPadding;
263	RTSEL cs;
264	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
265
266	union
267	{
268	X86EFLAGS eflags;
269	X86RFLAGS rflags;
270	};
271	union
272	{
273	uint16_t ip;
274	uint32_t eip;
275	uint64_t rip;
276	};
277
278	uint64_t r8;
279	uint64_t r9;
280	uint64_t r10;
281	uint64_t r11;
282	uint64_t r12;
283	uint64_t r13;
284	uint64_t r14;
285	uint64_t r15;
286
287	/** Hidden selector registers.
288	* @{ */
289	CPUMSELREGHID esHid;
290	CPUMSELREGHID csHid;
291	CPUMSELREGHID ssHid;
292	CPUMSELREGHID dsHid;
293	CPUMSELREGHID fsHid;
294	CPUMSELREGHID gsHid;
295	/** @} */
296
297	/** @} */
298
299	/** Control registers.
300	* @{ */
301	uint64_t cr0;
302	uint64_t cr2;
303	uint64_t cr3;
304	uint64_t cr4;
305	/** @} */
306
307	/** Debug registers.
308	* @remarks DR4 and DR5 should not be used since they are aliases for
309	* DR6 and DR7 respectively on both AMD and Intel CPUs.
310	* @remarks DR8-15 are currently not supported by AMD or Intel, so
311	* neither do we.
312	* @{ */
313	uint64_t dr[8];
314	/** @} */
315
316	/** Global Descriptor Table register. */
317	VBOXGDTR gdtr;
318	uint16_t gdtrPadding;
319	/** Interrupt Descriptor Table register. */
320	VBOXIDTR idtr;
321	uint16_t idtrPadding;
322	/** The task register.
323	* Only the guest context uses all the members. */
324	RTSEL ldtr;
325	RTSEL ldtrPadding;
326	/** The task register.
327	* Only the guest context uses all the members. */
328	RTSEL tr;
329	RTSEL trPadding;
330
331	/** The sysenter msr registers.
332	* This member is not used by the hypervisor context. */
333	CPUMSYSENTER SysEnter;
334
335	/** System MSRs.
336	* @{ */
337	uint64_t msrEFER;
338	uint64_t msrSTAR; /* legacy syscall eip, cs & ss */
339	uint64_t msrPAT;
340	uint64_t msrLSTAR; /* 64 bits mode syscall rip */
341	uint64_t msrCSTAR; /* compatibility mode syscall rip */
342	uint64_t msrSFMASK; /* syscall flag mask */
343	uint64_t msrKERNELGSBASE;/* swapgs exchange value */
344	/** @} */
345
346	/** Hidden selector registers.
347	* @{ */
348	CPUMSELREGHID ldtrHid;
349	CPUMSELREGHID trHid;
350	/** @} */
351
352	#if 0
353	/& Padding to align the size on a 64 byte boundrary. /
354	uint32_t padding[6];
355	#endif
356	} CPUMCTX;
357	#pragma pack()
358
359	/**
360	* Gets the CPUMCTXCORE part of a CPUMCTX.
361	*/
362	#define CPUMCTX2CORE(pCtx) ((PCPUMCTXCORE)(void *)&(pCtx)->edi)
363
364	/**
365	* Selector hidden registers, for version 1.6 saved state.
366	*/
367	typedef struct CPUMSELREGHID_VER1_6
368	{
369	/** Base register. */
370	uint32_t u32Base;
371	/** Limit (expanded). */
372	uint32_t u32Limit;
373	/** Flags.
374	* This is the high 32-bit word of the descriptor entry.
375	* Only the flags, dpl and type are used. */
376	X86DESCATTR Attr;
377	} CPUMSELREGHID_VER1_6;
378
379	/**
380	* CPU context, for version 1.6 saved state.
381	* @remarks PATM uses this, which is why it has to be here.
382	*/
383	#pragma pack(1)
384	typedef struct CPUMCTX_VER1_6
385	{
386	/** FPU state. (16-byte alignment)
387	* @todo This doesn't have to be in X86FXSTATE on CPUs without fxsr - we need a type for the
388	* actual format or convert it (waste of time). */
389	X86FXSTATE fpu;
390
391	/** CPUMCTXCORE Part.
392	* @{ */
393	union
394	{
395	uint32_t edi;
396	uint64_t rdi;
397	};
398	union
399	{
400	uint32_t esi;
401	uint64_t rsi;
402	};
403	union
404	{
405	uint32_t ebp;
406	uint64_t rbp;
407	};
408	union
409	{
410	uint32_t eax;
411	uint64_t rax;
412	};
413	union
414	{
415	uint32_t ebx;
416	uint64_t rbx;
417	};
418	union
419	{
420	uint32_t edx;
421	uint64_t rdx;
422	};
423	union
424	{
425	uint32_t ecx;
426	uint64_t rcx;
427	};
428	/* Note: we rely on the exact layout, because we use lss esp, [] in the switcher */
429	uint32_t esp;
430	RTSEL ss;
431	RTSEL ssPadding;
432	/* Note: no overlap with esp here. */
433	uint64_t rsp_notused;
434
435	RTSEL gs;
436	RTSEL gsPadding;
437	RTSEL fs;
438	RTSEL fsPadding;
439	RTSEL es;
440	RTSEL esPadding;
441	RTSEL ds;
442	RTSEL dsPadding;
443	RTSEL cs;
444	RTSEL csPadding[3]; /* 3 words to force 8 byte alignment for the remainder */
445
446	union
447	{
448	X86EFLAGS eflags;
449	X86RFLAGS rflags;
450	};
451	union
452	{
453	uint32_t eip;
454	uint64_t rip;
455	};
456
457	uint64_t r8;
458	uint64_t r9;
459	uint64_t r10;
460	uint64_t r11;
461	uint64_t r12;
462	uint64_t r13;
463	uint64_t r14;
464	uint64_t r15;
465
466	/** Hidden selector registers.
467	* @{ */
468	CPUMSELREGHID_VER1_6 esHid;
469	CPUMSELREGHID_VER1_6 csHid;
470	CPUMSELREGHID_VER1_6 ssHid;
471	CPUMSELREGHID_VER1_6 dsHid;
472	CPUMSELREGHID_VER1_6 fsHid;
473	CPUMSELREGHID_VER1_6 gsHid;
474	/** @} */
475
476	/** @} */
477
478	/** Control registers.
479	* @{ */
480	uint64_t cr0;
481	uint64_t cr2;
482	uint64_t cr3;
483	uint64_t cr4;
484	uint64_t cr8;
485	/** @} */
486
487	/** Debug registers.
488	* @{ */
489	uint64_t dr0;
490	uint64_t dr1;
491	uint64_t dr2;
492	uint64_t dr3;
493	uint64_t dr4; /*< @todo remove dr4 and dr5. /
494	uint64_t dr5;
495	uint64_t dr6;
496	uint64_t dr7;
497	/* DR8-15 are currently not supported */
498	/** @} */
499
500	/** Global Descriptor Table register. */
501	VBOXGDTR_VER1_6 gdtr;
502	uint16_t gdtrPadding;
503	uint32_t gdtrPadding64;/** @todo fix this hack */
504	/** Interrupt Descriptor Table register. */
505	VBOXIDTR_VER1_6 idtr;
506	uint16_t idtrPadding;
507	uint32_t idtrPadding64;/** @todo fix this hack */
508	/** The task register.
509	* Only the guest context uses all the members. */
510	RTSEL ldtr;
511	RTSEL ldtrPadding;
512	/** The task register.
513	* Only the guest context uses all the members. */
514	RTSEL tr;
515	RTSEL trPadding;
516
517	/** The sysenter msr registers.
518	* This member is not used by the hypervisor context. */
519	CPUMSYSENTER SysEnter;
520
521	/** System MSRs.
522	* @{ */
523	uint64_t msrEFER;
524	uint64_t msrSTAR;
525	uint64_t msrPAT;
526	uint64_t msrLSTAR;
527	uint64_t msrCSTAR;
528	uint64_t msrSFMASK;
529	uint64_t msrFSBASE;
530	uint64_t msrGSBASE;
531	uint64_t msrKERNELGSBASE;
532	/** @} */
533
534	/** Hidden selector registers.
535	* @{ */
536	CPUMSELREGHID_VER1_6 ldtrHid;
537	CPUMSELREGHID_VER1_6 trHid;
538	/** @} */
539
540	/* padding to get 32byte aligned size */
541	uint32_t padding[2];
542	} CPUMCTX_VER1_6;
543	#pragma pack()
544
545	/* Guest MSR state. */
546	typedef union CPUMCTXMSR
547	{
548	struct
549	{
550	uint64_t tscAux; /* MSR_K8_TSC_AUX */
551	} msr;
552	uint64_t au64[64];
553	} CPUMCTXMSR;
554	/** Pointer to the guest MSR state. */
555	typedef CPUMCTXMSR *PCPUMCTXMSR;
556	/** Pointer to the const guest MSR state. */
557	typedef const CPUMCTXMSR *PCCPUMCTXMSR;
558
559
560	/**
561	* The register set returned by a CPUID operation.
562	*/
563	typedef struct CPUMCPUID
564	{
565	uint32_t eax;
566	uint32_t ebx;
567	uint32_t ecx;
568	uint32_t edx;
569	} CPUMCPUID;
570	/** Pointer to a CPUID leaf. */
571	typedef CPUMCPUID *PCPUMCPUID;
572	/** Pointer to a const CPUID leaf. */
573	typedef const CPUMCPUID *PCCPUMCPUID;
574
575	/**
576	* CPUID feature to set or clear.
577	*/
578	typedef enum CPUMCPUIDFEATURE
579	{
580	CPUMCPUIDFEATURE_INVALID = 0,
581	/** The APIC feature bit. (Std+Ext) */
582	CPUMCPUIDFEATURE_APIC,
583	/** The sysenter/sysexit feature bit. (Std) */
584	CPUMCPUIDFEATURE_SEP,
585	/** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
586	CPUMCPUIDFEATURE_SYSCALL,
587	/** The PAE feature bit. (Std+Ext) */
588	CPUMCPUIDFEATURE_PAE,
589	/** The NXE feature bit. (Ext) */
590	CPUMCPUIDFEATURE_NXE,
591	/** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
592	CPUMCPUIDFEATURE_LAHF,
593	/** The LONG MODE feature bit. (Ext) */
594	CPUMCPUIDFEATURE_LONG_MODE,
595	/** The PAT feature bit. (Std+Ext) */
596	CPUMCPUIDFEATURE_PAT,
597	/** The x2APIC feature bit. (Std) */
598	CPUMCPUIDFEATURE_X2APIC,
599	/** The RDTSCP feature bit. (Ext) */
600	CPUMCPUIDFEATURE_RDTSCP,
601	/** 32bit hackishness. */
602	CPUMCPUIDFEATURE_32BIT_HACK = 0x7fffffff
603	} CPUMCPUIDFEATURE;
604
605	/**
606	* CPU Vendor.
607	*/
608	typedef enum CPUMCPUVENDOR
609	{
610	CPUMCPUVENDOR_INVALID = 0,
611	CPUMCPUVENDOR_INTEL,
612	CPUMCPUVENDOR_AMD,
613	CPUMCPUVENDOR_VIA,
614	CPUMCPUVENDOR_UNKNOWN,
615	/** 32bit hackishness. */
616	CPUMCPUVENDOR_32BIT_HACK = 0x7fffffff
617	} CPUMCPUVENDOR;
618
619
620	/** @name Guest Register Getters.
621	* @{ */
622	VMMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR);
623	VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit);
624	VMMDECL(RTSEL) CPUMGetGuestTR(PVM pVM);
625	VMMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM);
626	VMMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM);
627	VMMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM);
628	VMMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM);
629	VMMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM);
630	VMMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue);
631	VMMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM);
632	VMMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM);
633	VMMDECL(uint64_t) CPUMGetGuestRIP(PVM pVM);
634	VMMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM);
635	VMMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM);
636	VMMDECL(uint32_t) CPUMGetGuestECX(PVM pVM);
637	VMMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM);
638	VMMDECL(uint32_t) CPUMGetGuestESI(PVM pVM);
639	VMMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM);
640	VMMDECL(uint32_t) CPUMGetGuestESP(PVM pVM);
641	VMMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM);
642	VMMDECL(RTSEL) CPUMGetGuestCS(PVM pVM);
643	VMMDECL(RTSEL) CPUMGetGuestDS(PVM pVM);
644	VMMDECL(RTSEL) CPUMGetGuestES(PVM pVM);
645	VMMDECL(RTSEL) CPUMGetGuestFS(PVM pVM);
646	VMMDECL(RTSEL) CPUMGetGuestGS(PVM pVM);
647	VMMDECL(RTSEL) CPUMGetGuestSS(PVM pVM);
648	VMMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM);
649	VMMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM);
650	VMMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM);
651	VMMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM);
652	VMMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM);
653	VMMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM);
654	VMMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue);
655	VMMDECL(void) CPUMGetGuestCpuId(PVM pVM, uint32_t iLeaf, uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx);
656	VMMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdStdRCPtr(PVM pVM);
657	VMMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtRCPtr(PVM pVM);
658	VMMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurRCPtr(PVM pVM);
659	VMMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefRCPtr(PVM pVM);
660	VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM);
661	VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM);
662	VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
663	VMMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM);
664	VMMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM);
665	VMMDECL(uint64_t) CPUMGetGuestMsr(PVM pVM, unsigned idMsr);
666	VMMDECL(void) CPUMSetGuestMsr(PVM pVM, unsigned idMsr, uint64_t valMsr);
667	/** @} */
668
669	/** @name Guest Register Setters.
670	* @{ */
671	VMMDECL(int) CPUMSetGuestGDTR(PVM pVM, uint32_t addr, uint16_t limit);
672	VMMDECL(int) CPUMSetGuestIDTR(PVM pVM, uint32_t addr, uint16_t limit);
673	VMMDECL(int) CPUMSetGuestTR(PVM pVM, uint16_t tr);
674	VMMDECL(int) CPUMSetGuestLDTR(PVM pVM, uint16_t ldtr);
675	VMMDECL(int) CPUMSetGuestCR0(PVM pVM, uint64_t cr0);
676	VMMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2);
677	VMMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3);
678	VMMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4);
679	VMMDECL(int) CPUMSetGuestDR0(PVM pVM, uint64_t uDr0);
680	VMMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1);
681	VMMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2);
682	VMMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3);
683	VMMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6);
684	VMMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7);
685	VMMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value);
686	VMMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags);
687	VMMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip);
688	VMMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax);
689	VMMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx);
690	VMMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx);
691	VMMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx);
692	VMMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi);
693	VMMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi);
694	VMMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp);
695	VMMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp);
696	VMMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs);
697	VMMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds);
698	VMMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es);
699	VMMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs);
700	VMMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs);
701	VMMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss);
702	VMMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val);
703	VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
704	VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
705	VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
706	VMMDECL(void) CPUMSetGuestCtx(PVM pVM, const PCPUMCTX pCtx);
707	/** @} */
708
709	/** @name Misc Guest Predicate Functions.
710	* @{ */
711
712
713	VMMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
714	VMMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
715	VMMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
716
717	/**
718	* Tests if the guest is running in real mode or not.
719	*
720	* @returns true if in real mode, otherwise false.
721	* @param pVM The VM handle.
722	*/
723	DECLINLINE(bool) CPUMIsGuestInRealMode(PVM pVM)
724	{
725	return !(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
726	}
727
728	/**
729	* Tests if the guest is running in real mode or not.
730	*
731	* @returns true if in real mode, otherwise false.
732	* @param pCtx Current CPU context
733	*/
734	DECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
735	{
736	return !(pCtx->cr0 & X86_CR0_PE);
737	}
738
739	/**
740	* Tests if the guest is running in protected or not.
741	*
742	* @returns true if in protected mode, otherwise false.
743	* @param pVM The VM handle.
744	*/
745	DECLINLINE(bool) CPUMIsGuestInProtectedMode(PVM pVM)
746	{
747	return !!(CPUMGetGuestCR0(pVM) & X86_CR0_PE);
748	}
749
750	/**
751	* Tests if the guest is running in paged protected or not.
752	*
753	* @returns true if in paged protected mode, otherwise false.
754	* @param pVM The VM handle.
755	*/
756	DECLINLINE(bool) CPUMIsGuestInPagedProtectedMode(PVM pVM)
757	{
758	return (CPUMGetGuestCR0(pVM) & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
759	}
760
761	/**
762	* Tests if the guest is running in paged protected or not.
763	*
764	* @returns true if in paged protected mode, otherwise false.
765	* @param pVM The VM handle.
766	*/
767	DECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
768	{
769	return (pCtx->cr0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG);
770	}
771
772	/**
773	* Tests if the guest is running in long mode or not.
774	*
775	* @returns true if in long mode, otherwise false.
776	* @param pVM The VM handle.
777	*/
778	DECLINLINE(bool) CPUMIsGuestInLongMode(PVM pVM)
779	{
780	return (CPUMGetGuestEFER(pVM) & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
781	}
782
783	/**
784	* Tests if the guest is running in long mode or not.
785	*
786	* @returns true if in long mode, otherwise false.
787	* @param pCtx Current CPU context
788	*/
789	DECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
790	{
791	return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
792	}
793
794	/**
795	* Tests if the guest is running in 64 bits mode or not.
796	*
797	* @returns true if in 64 bits protected mode, otherwise false.
798	* @param pVM The VM handle.
799	* @param pCtx Current CPU context
800	*/
801	DECLINLINE(bool) CPUMIsGuestIn64BitCode(PVM pVM, PCCPUMCTXCORE pCtx)
802	{
803	if (!CPUMIsGuestInLongMode(pVM))
804	return false;
805
806	return pCtx->csHid.Attr.n.u1Long;
807	}
808
809	/**
810	* Tests if the guest is running in 64 bits mode or not.
811	*
812	* @returns true if in 64 bits protected mode, otherwise false.
813	* @param pVM The VM handle.
814	* @param pCtx Current CPU context
815	*/
816	DECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCCPUMCTX pCtx)
817	{
818	if (!(pCtx->msrEFER & MSR_K6_EFER_LMA))
819	return false;
820
821	return pCtx->csHid.Attr.n.u1Long;
822	}
823
824	/**
825	* Tests if the guest is running in PAE mode or not.
826	*
827	* @returns true if in PAE mode, otherwise false.
828	* @param pCtx Current CPU context
829	*/
830	DECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
831	{
832	return ( CPUMIsGuestInPagedProtectedModeEx(pCtx)
833	&& (pCtx->cr4 & X86_CR4_PAE)
834	&& !CPUMIsGuestInLongModeEx(pCtx));
835	}
836
837	/** @} */
838
839
840	/** @name Hypervisor Register Getters.
841	* @{ */
842	VMMDECL(RTSEL) CPUMGetHyperCS(PVM pVM);
843	VMMDECL(RTSEL) CPUMGetHyperDS(PVM pVM);
844	VMMDECL(RTSEL) CPUMGetHyperES(PVM pVM);
845	VMMDECL(RTSEL) CPUMGetHyperFS(PVM pVM);
846	VMMDECL(RTSEL) CPUMGetHyperGS(PVM pVM);
847	VMMDECL(RTSEL) CPUMGetHyperSS(PVM pVM);
848	#if 0 /* these are not correct. */
849	VMMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM);
850	VMMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM);
851	VMMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM);
852	VMMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM);
853	#endif
854	/** This register is only saved on fatal traps. */
855	VMMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM);
856	VMMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM);
857	/** This register is only saved on fatal traps. */
858	VMMDECL(uint32_t) CPUMGetHyperECX(PVM pVM);
859	/** This register is only saved on fatal traps. */
860	VMMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM);
861	VMMDECL(uint32_t) CPUMGetHyperESI(PVM pVM);
862	VMMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM);
863	VMMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM);
864	VMMDECL(uint32_t) CPUMGetHyperESP(PVM pVM);
865	VMMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM);
866	VMMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM);
867	VMMDECL(uint64_t) CPUMGetHyperRIP(PVM pVM);
868	VMMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit);
869	VMMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit);
870	VMMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM);
871	VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM);
872	VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM);
873	VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM);
874	VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM);
875	VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM);
876	VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM);
877	VMMDECL(void) CPUMGetHyperCtx(PVM pVM, PCPUMCTX pCtx);
878	/** @} */
879
880	/** @name Hypervisor Register Setters.
881	* @{ */
882	VMMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit);
883	VMMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR);
884	VMMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit);
885	VMMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3);
886	VMMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR);
887	VMMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS);
888	VMMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS);
889	VMMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelDS);
890	VMMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelDS);
891	VMMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelDS);
892	VMMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS);
893	VMMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP);
894	VMMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl);
895	VMMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP);
896	VMMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0);
897	VMMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1);
898	VMMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2);
899	VMMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3);
900	VMMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6);
901	VMMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7);
902	VMMDECL(void) CPUMSetHyperCtx(PVM pVM, const PCPUMCTX pCtx);
903	VMMDECL(int) CPUMRecalcHyperDRx(PVM pVM);
904	/** @} */
905
906	VMMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
907	VMMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
908	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVM pVM);
909	VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtrEx(PVM pVM, PVMCPU pVCpu);
910	VMMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
911	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
912	VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCoreEx(PVM pVM, PVMCPU pVCpu);
913	VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
914	VMMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
915	VMMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
916	VMMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
917	VMMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
918	VMMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
919	VMMDECL(int) CPUMHandleLazyFPU(PVM pVM, PVMCPU pVCpu);
920
921	/** @name Changed flags
922	* These flags are used to keep track of which important register that
923	* have been changed since last they were reset. The only one allowed
924	* to clear them is REM!
925	* @{
926	*/
927	#define CPUM_CHANGED_FPU_REM RT_BIT(0)
928	#define CPUM_CHANGED_CR0 RT_BIT(1)
929	#define CPUM_CHANGED_CR4 RT_BIT(2)
930	#define CPUM_CHANGED_GLOBAL_TLB_FLUSH RT_BIT(3)
931	#define CPUM_CHANGED_CR3 RT_BIT(4)
932	#define CPUM_CHANGED_GDTR RT_BIT(5)
933	#define CPUM_CHANGED_IDTR RT_BIT(6)
934	#define CPUM_CHANGED_LDTR RT_BIT(7)
935	#define CPUM_CHANGED_TR RT_BIT(8)
936	#define CPUM_CHANGED_SYSENTER_MSR RT_BIT(9)
937	#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10)
938	#define CPUM_CHANGED_CPUID RT_BIT(11)
939	#define CPUM_CHANGED_ALL (CPUM_CHANGED_FPU_REM\|CPUM_CHANGED_CR0\|CPUM_CHANGED_CR3\|CPUM_CHANGED_CR4\|CPUM_CHANGED_GDTR\|CPUM_CHANGED_IDTR\|CPUM_CHANGED_LDTR\|CPUM_CHANGED_TR\|CPUM_CHANGED_SYSENTER_MSR\|CPUM_CHANGED_HIDDEN_SEL_REGS\|CPUM_CHANGED_CPUID)
940	/** @} */
941
942	VMMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
943	VMMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
944	VMMDECL(bool) CPUMSupportsFXSR(PVM pVM);
945	VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
946	VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
947	VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCPU);
948	VMMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
949	VMMDECL(bool) CPUMIsGuestDebugStateActive(PVM pVM);
950	VMMDECL(void) CPUMDeactivateGuestDebugState(PVM pVM);
951	VMMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
952	VMMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
953	VMMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
954
955	/**
956	* CPU modes.
957	*/
958	typedef enum CPUMMODE
959	{
960	/** The usual invalid zero entry. */
961	CPUMMODE_INVALID = 0,
962	/** Real mode. */
963	CPUMMODE_REAL,
964	/** Protected mode (32-bit). */
965	CPUMMODE_PROTECTED,
966	/** Long mode (64-bit). */
967	CPUMMODE_LONG
968	} CPUMMODE;
969
970	VMMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
971
972
973	#ifdef IN_RING3
974	/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
975	* @ingroup grp_cpum
976	* @{
977	*/
978
979	VMMR3DECL(int) CPUMR3Init(PVM pVM);
980	VMMR3DECL(int) CPUMR3InitCPU(PVM pVM);
981	VMMR3DECL(void) CPUMR3Relocate(PVM pVM);
982	VMMR3DECL(int) CPUMR3Term(PVM pVM);
983	VMMR3DECL(int) CPUMR3TermCPU(PVM pVM);
984	VMMR3DECL(void) CPUMR3Reset(PVM pVM);
985	# ifdef DEBUG
986	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
987	# endif
988	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
989
990	/** @} */
991	#endif /* IN_RING3 */
992
993	#ifdef IN_RC
994	/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
995	* @ingroup grp_cpum
996	* @{
997	*/
998
999	/**
1000	* Calls a guest trap/interrupt handler directly
1001	* Assumes a trap stack frame has already been setup on the guest's stack!
1002	*
1003	* @param pRegFrame Original trap/interrupt context
1004	* @param selCS Code selector of handler
1005	* @param pHandler GC virtual address of handler
1006	* @param eflags Callee's EFLAGS
1007	* @param selSS Stack selector for handler
1008	* @param pEsp Stack address for handler
1009	*
1010	* This function does not return!
1011	*/
1012	DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
1013	VMMRCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
1014
1015	/** @} */
1016	#endif /* IN_RC */
1017
1018	#ifdef IN_RING0
1019	/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
1020	* @ingroup grp_cpum
1021	* @{
1022	*/
1023	VMMR0DECL(int) CPUMR0Init(PVM pVM);
1024	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1025	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1026	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
1027	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6);
1028
1029	/** @} */
1030	#endif /* IN_RING0 */
1031
1032	/** @} */
1033	__END_DECLS
1034
1035
1036	#endif
1037

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source: vbox/trunk/include/VBox/cpum.h@ 14972

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