VirtualBox

source: vbox/trunk/include/VBox/apic.mac@ 93115

Last change on this file since 93115 was 93115, checked in by vboxsync, 3 years ago

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1;; @file
2; X86 (and AMD64) Local APIC registers (VMM,++).
3;
4; Automatically generated by various.sed. DO NOT EDIT!
5;
6
7;
8; Copyright (C) 2010-2022 Oracle Corporation
9;
10; This file is part of VirtualBox Open Source Edition (OSE), as
11; available from http://www.virtualbox.org. This file is free software;
12; you can redistribute it and/or modify it under the terms of the GNU
13; General Public License (GPL) as published by the Free Software
14; Foundation, in version 2 as it comes in the "COPYING" file of the
15; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17;
18; The contents of this file may alternatively be used under the terms
19; of the Common Development and Distribution License Version 1.0
20; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21; VirtualBox OSE distribution, in which case the provisions of the
22; CDDL are applicable instead of those of the GPL.
23;
24; You may elect to license modified versions of this file under the
25; terms and conditions of either the GPL or the CDDL or both.
26;
27
28%ifndef VBOX_INCLUDED_apic_h
29%define VBOX_INCLUDED_apic_h
30%ifndef RT_WITHOUT_PRAGMA_ONCE
31%endif
32%define APIC_REG_VERSION 0x0030
33%define APIC_REG_VERSION_GET_VER(u32) (u32 & 0xff)
34%define APIC_REG_VERSION_GET_MAX_LVT(u32) ((u32 & 0xff0000) >> 16)
35%define APIC_REG_LVT_LINT0 0x0350
36%define APIC_REG_LVT_LINT1 0x0360
37%define APIC_REG_LVT_ERR 0x0370
38%define APIC_REG_LVT_PC 0x0340
39%define APIC_REG_LVT_THMR 0x0330
40%define APIC_REG_LVT_CMCI 0x02F0
41%define APIC_REG_EILVT0 0x0500
42%define APIC_REG_EILVT1 0x0510
43%define APIC_REG_EILVT2 0x0520
44%define APIC_REG_EILVT3 0x0530
45%define APIC_REG_LVT_MODE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
46%define APIC_REG_LVT_MODE_FIXED 0
47%define APIC_REG_LVT_MODE_NMI RT_BIT(10)
48%define APIC_REG_LVT_MODE_EXTINT (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
49%define APIC_REG_LVT_PIN_POLARIY RT_BIT(13)
50%define APIC_REG_LVT_REMOTE_IRR RT_BIT(14)
51%define APIC_REG_LVT_LEVEL_TRIGGER RT_BIT(15)
52%define APIC_REG_LVT_MASKED RT_BIT(16)
53%define XAPIC_HARDWARE_VERSION_P4 0x14
54%define XAPIC_MAX_LVT_ENTRIES_P4 6
55%define XAPIC_APIC_ID_BIT_COUNT_P4 8
56%define XAPIC_HARDWARE_VERSION_P6 0x10
57%define XAPIC_MAX_LVT_ENTRIES_P6 4
58%define XAPIC_APIC_ID_BIT_COUNT_P6 4
59%define XAPIC_ILLEGAL_VECTOR_START 0
60%define XAPIC_ILLEGAL_VECTOR_END 15
61%define XAPIC_RSVD_VECTOR_START 16
62%define XAPIC_RSVD_VECTOR_END 31
63 %define XAPIC_ESR_SEND_CHKSUM_ERROR_P6 RT_BIT(0)
64 %define XAPIC_ESR_RECV_CHKSUM_ERROR_P6 RT_BIT(1)
65 %define XAPIC_ESR_SEND_ACCEPT_ERROR_P6 RT_BIT(2)
66 %define XAPIC_ESR_RECV_ACCEPT_ERROR_P6 RT_BIT(3)
67%define XAPIC_ESR_REDIRECTABLE_IPI RT_BIT(4)
68%define XAPIC_ESR_SEND_ILLEGAL_VECTOR RT_BIT(5)
69%define XAPIC_ESR_RECV_ILLEGAL_VECTOR RT_BIT(6)
70%define XAPIC_ESR_ILLEGAL_REG_ADDRESS RT_BIT(7)
71%define XAPIC_ESR_WO_VALID 0x0
72%define XAPIC_TPR_VALID 0xff
73%define XAPIC_TPR_TP 0xf0
74%define XAPIC_TPR_TP_SUBCLASS 0x0f
75%define XAPIC_TPR_GET_TP(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP)
76%define XAPIC_TPR_GET_TP_SUBCLASS(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP_SUBCLASS)
77%define XAPIC_PPR_VALID 0xff
78%define XAPIC_PPR_PP 0xf0
79%define XAPIC_PPR_PP_SUBCLASS 0x0f
80%define XAPIC_PPR_GET_PP(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP)
81%define XAPIC_PPR_GET_PP_SUBCLASS(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP_SUBCLASS)
82%define XAPIC_TIMER_MODE_ONESHOT 0
83%define XAPIC_TIMER_MODE_PERIODIC 1
84%define XAPIC_TIMER_MODE_TSC_DEADLINE 2
85%define XAPIC_LVT_VECTOR 0xff
86%define XAPIC_LVT_GET_VECTOR(a_Lvt) ((a_Lvt) & XAPIC_LVT_VECTOR)
87%define XAPIC_LVT_MASK RT_BIT(16)
88%define XAPIC_LVT_IS_MASKED(a_Lvt) RT_BOOL((a_Lvt) & XAPIC_LVT_MASK)
89%define XAPIC_LVT_TIMER_MODE RT_BIT(17)
90%define XAPIC_LVT_TIMER_TSCDEADLINE RT_BIT(18)
91%define XAPIC_LVT_GET_TIMER_MODE(a_Lvt) (XAPICTIMERMODE)(((a_Lvt) >> 17) & 3)
92%define XAPIC_LVT_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
93%define XAPIC_LVT_GET_DELIVERY_MODE(a_Lvt) (XAPICDELIVERYMODE)(((a_Lvt) >> 8) & 7)
94%define XAPIC_LVT_DELIVERY_STATUS RT_BIT(12)
95%define XAPIC_LVT_TRIGGER_MODE RT_BIT(15)
96%define XAPIC_LVT_GET_TRIGGER_MODE(a_Lvt) (XAPICTRIGGERMODE)(((a_Lvt) >> 15) & 1)
97%define XAPIC_LVT_REMOTE_IRR RT_BIT(14)
98%define XAPIC_LVT_GET_REMOTE_IRR(a_Lvt) (((a_Lvt) >> 14) & 1)
99%define XAPIC_LVT_POLARITY RT_BIT(13)
100%define XAPIC_LVT_GET_POLARITY(a_Lvt) (((a_Lvt) >> 13) & 1)
101%define XAPIC_LVT_COMMON_VALID (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK)
102%define XAPIC_LVT_CMCI_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
103%define XAPIC_LVT_TIMER_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE)
104%define XAPIC_LVT_THERMAL_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
105%define XAPIC_LVT_PERF_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
106%define XAPIC_LVT_LINT_VALID ( XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \
107 | XAPIC_LVT_POLARITY | XAPIC_LVT_REMOTE_IRR | XAPIC_LVT_TRIGGER_MODE)
108%define XAPIC_LVT_ERROR_VALID (XAPIC_LVT_COMMON_VALID)
109%define XAPIC_SVR_VECTOR 0xff
110%define XAPIC_SVR_SOFTWARE_ENABLE RT_BIT(8)
111%define XAPIC_SVR_SUPRESS_EOI_BROADCAST RT_BIT(12)
112 %define XAPIC_SVR_VALID_P4 (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE)
113%define XAPIC_DFR_VALID 0xf0000000
114%define XAPIC_DFR_RSVD_MB1 0x0fffffff
115%define XAPIC_DFR_MODEL 0xf
116%define XAPIC_DFR_GET_MODEL(a_uReg) (((a_uReg) >> 28) & XAPIC_DFR_MODEL)
117%define XAPIC_LDR_VALID 0xff000000
118%define X2APIC_LDR_CLUSTER_ID 0xffff0000
119%define X2APIC_LDR_GET_CLUSTER_ID(a_uReg) ((a_uReg) & X2APIC_LDR_CLUSTER_ID)
120%define X2APIC_LDR_LOGICAL_ID 0x0000ffff
121%define XAPIC_LDR_FLAT_LOGICAL_ID 0xff
122%define XAPIC_LDR_CLUSTERED_CLUSTER_ID 0xf0
123%define XAPIC_LDR_CLUSTERED_LOGICAL_ID 0x0f
124%define XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(a_uReg) ((a_uReg) & XAPIC_LDR_CLUSTERED_CLUSTER_ID)
125%define XAPIC_EOI_WO_VALID 0x0
126%define XAPIC_TIMER_ICR_VALID 0xffffffff
127%define XAPIC_TIMER_DCR_VALID (RT_BIT(0) | RT_BIT(1) | RT_BIT(3))
128%define XAPIC_SELF_IPI_VALID 0xff
129%define XAPIC_SELF_IPI_VECTOR 0xff
130%define XAPIC_SELF_IPI_GET_VECTOR(a_uReg) ((a_uReg) & XAPIC_SELF_IPI_VECTOR)
131%define XAPIC_ICR_LO_VECTOR 0xff
132%define XAPIC_ICR_LO_GET_VECTOR(a_uIcr) ((a_uIcr) & XAPIC_ICR_LO_VECTOR)
133%define XAPIC_ICR_LO_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
134%define XAPIC_ICR_LO_DEST_MODE RT_BIT(11)
135%define XAPIC_ICR_LO_DELIVERY_STATUS RT_BIT(12)
136%define XAPIC_ICR_LO_LEVEL RT_BIT(14)
137%define XAPIC_ICR_TRIGGER_MODE RT_BIT(15)
138%define XAPIC_ICR_LO_DEST_SHORTHAND (RT_BIT(18) | RT_BIT(19))
139%define XAPIC_ICR_LO_WR_VALID ( XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \
140 | XAPIC_ICR_LO_LEVEL | XAPIC_ICR_TRIGGER_MODE | XAPIC_ICR_LO_DEST_SHORTHAND)
141%define XAPIC_ICR_HI_DEST 0xff000000
142%define XAPIC_ICR_HI_GET_DEST(a_u32IcrHi) (((a_u32IcrHi) >> 24) & XAPIC_ICR_HI_DEST)
143%define XAPIC_ICR_HI_WR_VALID XAPIC_ICR_HI_DEST
144%define X2APIC_ID_BROADCAST_MASK 0xffffffff
145 %define XAPIC_ID_BROADCAST_MASK_P4 0xff
146%define X2APIC_GET_XAPIC_OFF(a_uMsr) ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & 0xff0)
147%define XAPIC_GET_X2APIC_MSR(a_offReg) ((((a_offReg) & 0xff0) >> 4) | MSR_IA32_X2APIC_START)
148%define XAPIC_OFF_ID 0x020
149%define XAPIC_OFF_VERSION 0x030
150%define XAPIC_OFF_TPR 0x080
151%define XAPIC_OFF_APR 0x090
152%define XAPIC_OFF_PPR 0x0A0
153%define XAPIC_OFF_EOI 0x0B0
154%define XAPIC_OFF_RRD 0x0C0
155%define XAPIC_OFF_LDR 0x0D0
156%define XAPIC_OFF_DFR 0x0E0
157%define XAPIC_OFF_SVR 0x0F0
158%define XAPIC_OFF_ISR0 0x100
159%define XAPIC_OFF_ISR1 0x110
160%define XAPIC_OFF_ISR2 0x120
161%define XAPIC_OFF_ISR3 0x130
162%define XAPIC_OFF_ISR4 0x140
163%define XAPIC_OFF_ISR5 0x150
164%define XAPIC_OFF_ISR6 0x160
165%define XAPIC_OFF_ISR7 0x170
166%define XAPIC_OFF_TMR0 0x180
167%define XAPIC_OFF_TMR1 0x190
168%define XAPIC_OFF_TMR2 0x1A0
169%define XAPIC_OFF_TMR3 0x1B0
170%define XAPIC_OFF_TMR4 0x1C0
171%define XAPIC_OFF_TMR5 0x1D0
172%define XAPIC_OFF_TMR6 0x1E0
173%define XAPIC_OFF_TMR7 0x1F0
174%define XAPIC_OFF_IRR0 0x200
175%define XAPIC_OFF_IRR1 0x210
176%define XAPIC_OFF_IRR2 0x220
177%define XAPIC_OFF_IRR3 0x230
178%define XAPIC_OFF_IRR4 0x240
179%define XAPIC_OFF_IRR5 0x250
180%define XAPIC_OFF_IRR6 0x260
181%define XAPIC_OFF_IRR7 0x270
182%define XAPIC_OFF_ESR 0x280
183%define XAPIC_OFF_LVT_CMCI 0x2F0
184%define XAPIC_OFF_ICR_LO 0x300
185%define XAPIC_OFF_ICR_HI 0x310
186%define XAPIC_OFF_LVT_TIMER 0x320
187%define XAPIC_OFF_LVT_THERMAL 0x330
188%define XAPIC_OFF_LVT_PERF 0x340
189%define XAPIC_OFF_LVT_LINT0 0x350
190%define XAPIC_OFF_LVT_LINT1 0x360
191%define XAPIC_OFF_LVT_ERROR 0x370
192%define XAPIC_OFF_TIMER_ICR 0x380
193%define XAPIC_OFF_TIMER_CCR 0x390
194%define XAPIC_OFF_TIMER_DCR 0x3E0
195%define X2APIC_OFF_SELF_IPI 0x3F0
196%define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER
197%define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR
198%define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI
199%define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI
200%define XAPIC_OFF_END 0x3F0
201%ifdef IPRT_INCLUDED_asm_amd64_x86_h
202%endif
203%endif
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